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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Ian@SI who wrote (45451)	4/16/2001 11:13:04 AM
From: Shoibal Datta	Read Replies (2) \| Respond to of 70976

Moore's law will remain valid as long as chip usage and uses proliferate Ian, you raise an interesting point. Can you put the above statement in perspective with what is happening in Intel's PC or any other core chip businesses? Is the PC sector growing at a rate that justifies that kind of capital investment any more? In other words, should they invest a large amount of money in order to bring their cost structure down in an industry that is most likely not going to care? As an individual, would you be enthused about buying a P4 if the cost is reduced by $400 now. If the answer is no, then it doesn't much matter what Intel's cost is to make that chip. If the answer is yes, then Intel has a valid investment. As a corporation, is a P4 at any cost going to provide a significant advantage over the faster (and cheaper) P3s? As far as home consumers go, I think the bottleneck is not at the CPU level (and hasn't been for some time). I can easily justify wanting to buy the latest greatest graphics board for $350 rather than upgrading my CPU for the same amount. On the corporate side, a fast P3 will fulfill the needs of most desktops. Given this environment, making large-scale production buys in the capex department seems riskier. It would seem to me that it might make more sense to make small scale technology buys and feel this cycle out before making long term commitments. But then, I'm no techie. -SD

To: Ian@SI who wrote (45451)	4/16/2001 5:20:14 PM
From: Proud_Infidel	Respond to of 70976

Etching process shrinks design rules to 25 nanometers By R. Colin Johnson EE Times (04/16/01 14:16 p.m. EST) ITHACA, N.Y. — Cornell University researchers have discovered yet another method for shrinking the design rules on silicon chips. The researchers demonstrated the technique, called controlled etching of dislocations (CED), by crafting tiny silicon columns six times smaller than today's smallest features. The so-called nanobumps measured just 25 nanometers, or about 100 atoms, across. (A nanometer is close to the width of four silicon atoms.) "We have created silicon surface structures that can ultimately be used to build a variety of new device types," said Stephen Sass, professor of materials science. "With CED we may even be able to confine electrons in ways that allow them to emit light, even though normally silicon cannot be used to make LEDs or flat-panel displays," said Melissa Hines, associate professor of chemistry. The CED process starts with two identical polished silicon wafers instead of just one. The wafers are pressed against each other, slightly twisted at a precisely controlled angle and then bonded together to form what's called a bi-crystal. The identical rows of silicon atoms line up with one another where the rows cross, and the matchups form a tightly packed pattern across the wafer. At each point in the pattern where the silicon atoms line up, a strong silicon bond, called a grain boundary, is formed. Sass has studied grain boundaries, and the checkerboard pattern they form, for 30 years. By using a special etching solution of trioxide and hydrofluoric acid, Sass and Hines were able to wash away the weakly bonded atoms, called the dislocations, leaving only the strongly bonded nanobumps. For their demonstration, the researchers fabricated nanobumps approximately 100 atoms (25 nanometers) in diameter and 160 atoms (38 nanometers) apart using a fraction of a degree offset. By increasing the twist angle to 4°,the next-generation nanobumps could measure just 5.5 nm in width, or about 20 atoms. By contrast, chips produced with optical lithography are limited by the wavelength of light, enabling features no smaller than about 150 nm in width. "It is not the width of the nanobumps that matters so much as the distance between them. At an angle of 10°, we could theoretically space nanobumps only two nm apart" — about seven silicon atoms, said Hines. Besides making smaller chips, on-chip optical waveguides and eventually even silicon LEDs, the technique could further find use in the magnetic storage industry, which could employ the features for ultrahigh-density silicon disks, the researchers said. Such disks would deposit magnetic material atop each nanobump to create "domains" exceeding 1 billion bits/cm2.

To: Ian@SI who wrote (45451)	4/16/2001 5:27:39 PM
From: Proud_Infidel	Respond to of 70976

Etching process shrinks design rules to 25 nanometers By R. Colin Johnson EE Times (04/16/01 14:16 p.m. EST) ITHACA, N.Y. — Cornell University researchers have discovered yet another method for shrinking the design rules on silicon chips. The researchers demonstrated the technique, called controlled etching of dislocations (CED), by crafting tiny silicon columns six times smaller than today's smallest features. The so-called nanobumps measured just 25 nanometers, or about 100 atoms, across. (A nanometer is close to the width of four silicon atoms.) "We have created silicon surface structures that can ultimately be used to build a variety of new device types," said Stephen Sass, professor of materials science. "With CED we may even be able to confine electrons in ways that allow them to emit light, even though normally silicon cannot be used to make LEDs or flat-panel displays," said Melissa Hines, associate professor of chemistry. The CED process starts with two identical polished silicon wafers instead of just one. The wafers are pressed against each other, slightly twisted at a precisely controlled angle and then bonded together to form what's called a bi-crystal. The identical rows of silicon atoms line up with one another where the rows cross, and the matchups form a tightly packed pattern across the wafer. At each point in the pattern where the silicon atoms line up, a strong silicon bond, called a grain boundary, is formed. Sass has studied grain boundaries, and the checkerboard pattern they form, for 30 years. By using a special etching solution of trioxide and hydrofluoric acid, Sass and Hines were able to wash away the weakly bonded atoms, called the dislocations, leaving only the strongly bonded nanobumps. For their demonstration, the researchers fabricated nanobumps approximately 100 atoms (25 nanometers) in diameter and 160 atoms (38 nanometers) apart using a fraction of a degree offset. By increasing the twist angle to 4°,the next-generation nanobumps could measure just 5.5 nm in width, or about 20 atoms. By contrast, chips produced with optical lithography are limited by the wavelength of light, enabling features no smaller than about 150 nm in width. "It is not the width of the nanobumps that matters so much as the distance between them. At an angle of 10°, we could theoretically space nanobumps only two nm apart" — about seven silicon atoms, said Hines. Besides making smaller chips, on-chip optical waveguides and eventually even silicon LEDs, the technique could further find use in the magnetic storage industry, which could employ the features for ultrahigh-density silicon disks, the researchers said. Such disks would deposit magnetic material atop each nanobump to create "domains" exceeding 1 billion bits/cm2.