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To: kapkan4u who wrote (133635)4/29/2001 1:35:08 PM
From: Joseph Pareti  Read Replies (2) | Respond to of 186894
 
Re They wasted all these transistors to make the chip to run at high clock rates at the expense of IPC, only to discover that the future performance limitations are dominated by power delivery and dissipation.

As the L1 cache in future versions will be bigger (than 8KB)
the IPC rate will improve.

Do you still remember all the jokes when the first Celeron came out ? "celery", "pauleron", "a pentium with clipped wings", etc. Where is Celeron now ?



To: kapkan4u who wrote (133635)4/29/2001 10:12:38 PM
From: Paul Engel  Read Replies (1) | Respond to of 186894
 
Kal Kan - Re: " Time will tell. P4 designers went in the wrong direction. They wasted all these transistors to make the chip to run at high clock rates at the expense of IPC"

So far, you appear to be WRONG AGAIN !!

The Pentium 4 performs nearly as well as any AthWiper on business applications and beats the pants off the AthWipers in code written to optimize the P4 instruction set.

Time will tell - yes - but the indications are there for just what time will tell - and that is the Pentium 4 clock speed scales like hell and the SSE2 instructions will be adopted by more programs - and coupled with the ever increasing Pentium 4 clock speeds, the Intel CPU will dominate.

Throw in Intel's advanced 0.13 micron process and you have a triple whammy AGAINST AMD's one trick pony and smelly horsey-sh*t non-existent PaloMatHEad.

Back to the barn, for AMD.

Paul