To: Dan3 who wrote (133789 ) 5/1/2001 12:14:44 AM From: dale_laroy Read Replies (1) | Respond to of 186894 >I remember when all the AMD longs (including me) were expecting huge increases in AMD ASPs< Why? As soon as AMD announced that they would be marketing a value segment K7 processor prior to the move to 0.13-micron it was fairly obvious that ASP would not climb significantly. If AMD wanted climbing ASP they needed to segment their market into K6-2+(at 0.18-micron with copper interconnects) at the low end, and Athlon, primarily out of Austin, at the high end. > and were disappointed that AMD wasn't locking itself into huge expansion projects. Now, "suddenly," there is excess capacity as far as the eye can see, with a large number of new FABs coming on line in Taiwan, Korea, and Europe, and all the semi-commodity chips like flash and comm are facing brutal competition. So building new FABs for CPUs, and using the old FABs for those "other" purposes, once a great strategy, is now a great way to lose money.< How does this make less sense than building a new fab for flash (FASL 3) to begin ramp in 2002, while not planning on a 300mm wafer processor fab until 2004-2005? Prior to Intel introducing a value segment P4 processor, which will probably occur in 2003, AMD will have a free ride with using Fab25 to produce Duron processors. But once Intel introduces the value segment P4, AMD will be scrambling to convert Fab25 to flash production, and with no replacement for Fab25's capacity, AMD's market share will plummet. AMD needs a 300mm wafer Fab34 to begin ramp in 2003. This fab should ramp at the rate of four 0.13-micron 300mm wafer starts of production at Fab34 for every nine 200mm wafer starts at Fab25 lost to flash production. Ramp at 0.13-micron should continue until 40% capacity is reached just prior to the switch to 0.10-micron equipment, then AMD could build the rest of the way out to 90% ramp with 0.10-micron equipment. The final 10% of capacity ramp could be deferred until the installation of 0.07-micron equipment starts. >P4 will command a higher price, but keep hitting the ceiling of suspicious overall performance.< By 2003, it could be that P4 will have sufficient software that is friendly to its architecture that performance may not be an issue. The best way for AMD to delay this potential is to convince software developers that the total number of P4 processors will always be less than the total number of Athlon/Duron processors, even if AMD has to license Athlon/Duron to IBM and/or Motorola to insure that this is the case.