Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (71992)	5/4/2001 10:27:57 PM
From: cordob	Read Replies (2) \| Respond to of 93625

"The bus is relatively narrow, controlled impedance, and is terminated only at the end away from the controller." Thanks Bilow I am printing this as I am about to go to bed (after 4). I thought the signals on rdram were terminated both sides but will check. I am more impressed with the AMD HT scheme where the signals are differential, I think much higher speeds can be attained. Cheers Cor

To: Bilow who wrote (71992)	5/5/2001 1:37:50 AM
From: NightOwl	Read Replies (1) \| Respond to of 93625

Thanks for saving me the time Carl, I was just about to tell him the same thing.<vsg> 0\|0

To: Bilow who wrote (71992)	5/5/2001 5:59:03 AM
From: NightOwl	Read Replies (4) \| Respond to of 93625

OK Carl, Scumbria, Ali, et al: eet.com Part of HyperTransport's charm is its ability to remain transparent to the PCI bus, virtually guaranteeing compatibility with PCI-based products and preserving the huge OEM investment in that aging technology. "HyperTransport is done in such a way that it's been able to package PCI commands over a HyperTransport link so that drivers written to interface with devices over PCI can operate without modification," said Nathan Brookwood, president of market research firm Insight 64 (Saratoga, Calif.). "It [makes] the transition to a new standard a lot easier. It takes out all of the software issues because you've provided compatibility between the two environments." Bert McComas of InQuest market research (Higley, Ariz.) likened Intel's 3GIO approach to its backing of Rambus technology over double-data-rate (DDR) DRAM. In both cases, McComas claimed, Intel has sought to run interference against a competing, cost-effective spec to promote its own approach. "3GIO was a reaction," McComas said. "The industry was really dominantly moving toward HyperTransport, and Intel had to do something to run interference. But AMD's in the lead with this one. "Intel sees HyperTransport run out of the gate, and every horse out of the gate is going in that direction. So Intel wants to jump into the lead and throw itself against the traffic. Intel did the same thing with Rambus, throwing itself in front of DDR and saying, 'If you're big enough, c'mon and take me'." Intel's Gregory discounted that scenario, saying, "We have no interest in a bus war." But McComas argued that, "in a sense, every CPU war is a bus war." My questions for you EE wizards are: 1) Just how much of this well deserved ridicule is INTC going to put up with before it sends Gelsinger and all the other Bus Drivers packing? 2) When is AMD's 64 bit CPU coming and what's it called? 3) How much of INTC's market share in CPU's can AMD compete for, i.e., how much can they boost capacity while fighting INTC's giveaway of P4 ASP's? And most importantly of all, how can a company which is so "brand" and advertising conscious allow itself to be bound, for 7 more months, to a highly visible "partner" which is hated by so many elements in this industry and is in danger of being convicted of Fraud within the next week? I don't think the RMBS/INTC restrictive memory use Agreement will last the rest of the year whether INTC gets its DDR chip set out before year end or not. So what say you all? 0\|0

To: Bilow who wrote (71992)	5/5/2001 9:14:55 AM
From: gnuman	Read Replies (3) \| Respond to of 93625

Carl, re: The controller sees the bus impedance, but the RDRAM chips, since they are on the middle of the bus, see half the bus impedance. But both driver types are designed for the same output drive strength. Controller outputs drive down the bus and are absorbed by the termination at the other end. Since the bus is terminated, all chips see ZO/2 irrespective of position on the bus. The last chip on the bus certainly can't be characterized as being in the "middle of the bus." What's somewhat unusual is that RDRAM drives are half strength (in terms of voltage) because of the half impedance that the part sees in the middle of the bus. Two output signals propagate from the RDRAM, one half goes directly to the termination resistors and is absorbed. The other half is reflected at the controller end of the bus, and then travels back down the bus and is absorbed by the termination resistor. The voltage is doubled at the Controller since that end is un-terminated and hi- impedance. Because of the above, each RDRAM must drive a signal onto a floating bus. For this reason, the output is constructed as a current source, instead of the more usual voltage source. Floating bus? Explain that one, please. The bus is referenced to voltage, and through capacitors, to ground. If the bus were floating, wouldn't you expect severe issues of bias on the bus? As for using current source, the characteristics of the Rambus controlled impedance bus require it. And current source being very hi-impedance, it minimizes effects of reflections from the controller. Because of the fact that RDRAM outputs have to drive into their own (or worse yet, other chips') reflected output signals, it is not possible to hook an oscilloscope up to the RDRAM output to see the "eye diagram". Instead, the eye diagram for RDRAM outputs is only valid at the controller pin. Eye diagrams for controller driven signals are valid at each RDRAM pin, of course. Because the only place the "eye" is valid is at the controller pin, it makes no sense, (and is probably unintelligible), to look at an "eye" at the RDRAM output. JMO's