Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: muzosi who wrote (72452)	5/9/2001 11:53:44 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi muzosi; I've never used an RTL synthesis tool, but it makes a heck of a lot of sense to me. I like that RTL can be very close to the logic. One of my problems with using the PROCESS in VHDL is that it is constantly inferring memory (or latches) that you don't want. It used to be that I had to deal with that all the time. Since I started coding at a very low level, all my VHDL problems have been reduced to that of dealing with the verbosity of the stuff. Probably the primary result is that I can now type amazingly fast. The more modern schematic entry tools are so much improved from prior art that a lot of engineers are probably rejecting schematics for projects where it makes sense. My EE buddy (who sits at a workstation next to me), went back to schematics to connect up his VHDL blocks (after not doing any gate array or FPGA design work for a year or two), because it is such a pain to keep the instantiations straight with VHDL. I would like a tool that allows netlist entry for the parts of a design that just cry out for it, but still has RTL features. Is that too much to ask? I guess I feel reasonably happy with VHDL. -- Carl