Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: andreas_wonisch who wrote (44769)	6/20/2001 11:56:46 AM
From: jcholewa	Read Replies (1) \| Respond to of 275872

> But probably you are right since it says before "Table 29 > provides the thermal design power dissipation and maximum > temperatures". That would be extremely disappointing. That > would mean that TDP at 1.75 would be 40.6W for the 1.13 > GHz Tualatin. That's about the same (or even more?) than > the former 1.13 GHz Coppermine. I wonder how much more > power is consumed by the added 256kb L2 cache? It is possible that the 180nm process happens to already have the thermal advantages of the 130nm process, and that new process merely improves on the speedpaths. You know, there's supposed to be two ends of the process, and sometimes the current process is tweaked with elements of next generation processes. For example, AMD's jump from cs44e7 to cs50 helped their thermals but did not seem to have a huge initial impact on actual operating frequencies. It would suck, though, if Intel's jump from 180nm to 130nm did not help their power draw much. The Netburst family is somwhat heat limited in terms of frequency ramping, I have been told. -JC

To: andreas_wonisch who wrote (44769)	6/20/2001 1:22:40 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 275872

Andreas, from another document I've seen (but unfortunately isn't available to the public), the 27.9W figure is a max number, not a typical number. We'll find out more later. By the way, isn't the junction temperature of Athlon 4 specified to be 90 degrees C? The figure for Tualatin is 100 degrees, so Tualatin will need less cooling effort. Tenchusatsu

To: andreas_wonisch who wrote (44769)	6/20/2001 4:44:29 PM
From: Ali Chen	Respond to of 275872

Andreas, "The maximum power for each of these components does not occur simultaneously" It is simple. If you load 100% all internal CPU units with toggling data patterns (to get the max core power), you do not want to use any L2 walks, nor L2 misses. Therefore the L2 and bus consume nothing. To get the max dissipation on GTL lines, you generate huge L2 miss traffic, but it automatically implies that the core is most likely stalling. Same for L2. So, those max powers are mutually exclusive. Regards, - Ali