SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Charles R who wrote (45794)6/29/2001 5:04:27 PM
From: minnow68Read Replies (2) | Respond to of 275872
 
Chuck,

You wrote "I would also look at adding another 256K of cache to Athlon to segment the products better and to better compete with P4 (of course the assumption is that this would have no MHz penalty - if there is a MHz penalty then I would go with keeping things as they are today)."

There is always a Mhz penalty when adding non-trivial amounts of cache at the same level. That's why all the cache on existing chips isn't simply one huge L1 cache.

I've postulated for years that as processors shrink we will see increasing levels of cache on-chip. By levels, I do not mean size, I mean L1, L2, L3, etc.. I would not be surprised at all in 2010 to see the average processor have 16 Megabytes of on-chip cache organized in as many as half a dozen levels.

Mike



To: Charles R who wrote (45794)6/29/2001 5:52:42 PM
From: AK2004Respond to of 275872
 
Charles
hard to imagine that there is a demand for duron since lower end athlon systems are only few bucks more
Regards
-Albert