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To: minnow68 who wrote (45801)	6/29/2001 5:14:06 PM
From: Charles R	Read Replies (1) \| Respond to of 275872

Mike, <There is always a Mhz penalty when adding non-trivial amounts of cache at the same level. That's why all the cache on existing chips isn't simply one huge L1 cache.> Not true. If there is a MHz penalty or not is determined by where the speed paths in the chip are. Without knowing the specific timing details it is impossible to tell if there will be a problem. However, given a rather long latency L2 that you see on Athlons, I have a feeling that adding another 256k would not impact the speedpaths. Sorry, I don't have the patience to explain the cache timing mechanisms. Chuck

To: minnow68 who wrote (45801)	6/29/2001 11:12:17 PM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

>I would not be surprised at all in 2010 to see the average processor have 16 Megabytes of on-chip cache organized in as many as half a dozen levels.< There should be at least a factor of eight increase in cache size between levels. Thus, assuming 16MB in L4, there should be no more than 2MB in L3, 512KB in L2 and 64KB in L1. Of course, this assumes essentially the same architecture for each cache level. Radical differences, such as Harvard Architecture for L1, or going from two-way set associative to sixteen-way set associative could justify much less than eight times the amount of cache in L2 as in L1. Even so, it would be difficult to justify more than five levels with only 16MB of on-die cache at the lowest level.