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To: dale_laroy who wrote (45821)	6/30/2001 12:03:37 AM
From: minnow68	Read Replies (1) \| Respond to of 275872

Dale, You wrote "There should be at least a factor of eight increase in cache size between levels" With current technology, that's a reasonable rule of thumb. But die shrinks in the next decade will change some pretty fundamental aspects of processors. Imagine a processor the size of the P4 (217 square mm) running at 50 Ghz. A signal could not propagate from one end of the chip to another in a single clock cycle. This kind of thing will, IMHO, cause some pretty significant changes to how processors are designed (Indeed, the speeds already reached has caused new features that I've never before seen to show up, e.g. skew adjustment on the P4). Eventually, this may or may not include increasing how many levels of cache there are beyond current design concepts. In other words, I'm saying that until it is done, we can't know for sure what it will look like. I would not be surprised in the slightest if you are right and that 16 MB cache in a 50 Ghz processor will be in four levels. But I also won't be surprised if a cache like that winds up being a five or six level deep cache. Mike