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To: Charles R who wrote (47081)7/11/2001 2:19:00 AM
From: Paul EngelRead Replies (4) | Respond to of 275872
 
Re: "Do you have any links to show otherwise? "

How about 4 revisions - in 6 months?

amd.com

Product Errata

This section documents AMD-761™ system controller product errata. A unique tracking number for
each erratum has been assigned within this document for user convenience in tracking the errata
within specific revision levels. Table 2 cross-references the revisions of the controller to each erratum.
An “X” indicates that the erratum applies to the revision. The absence of an “X” indicates that the
erratum does not apply to the revision.
Note: There can be missing errata numbers. Errata that have been resolved from early revisions of the
controller have been deleted, and errata that have been reconsidered may have been deleted or
renumbered.
Table 2. Cross-Reference of Product Revision to Errata
Erratum Number and Description Revision
B0 B1 B2 B3
4 GART Requestors Do Not Work with TLB Caches Off X X X X
7 AGP Ordering Problem X X
31 External PCI Master to APC Target Resulted in an Extra Null Data Phase X X X X
37 Idle Cycle Limit Field Must be Non-Zero or ECC Scrubbing May Cause Failure X X X X
38 AGP Differential Strobe Inputs Must Be Controlled by AGP Command Register X
39 Writing to AGP Compensation Bypass Register Locks BIU Arbitration X X X X
41 AGP Failures During ACPI C1, C2 Power Management States X X
43 Voltage Sensitivity on VDD_CORE Causes AGP Failures X X X X
44 SYSCLK/AGPCLK Clock Skew Causes AGP-2X Failures X X
45 Timing Problem Prevents AGP Fast Writes Operation X X
46 Setup Violation on AGP SBA Pins X X
47 Extra Pulse on AGP Strobes X X
48 Memory Read Modify Write Data Corruption from AGP When Entering Self-Refresh in
C2/C3 Power Management States X XXX
49 Failure to Reconnect Following Exit From Self-Refresh X
51 Missed Refreshes When Burst Refresh is Enabled X X X X
52 False ACK When Switching from Two-Bit Time to Four-Bit Time Mode X X X X
53 Data Corruption Due to Switching Noise on Front-side Bus X X X X

23613C—May 2001 AMD-761™ System Controller Revision Guide
53 Data Corruption Due to Switching Noise on Front-side Bus
Products Affected. B0, B1, B2, B3
Description. InClk signals are corrupted by noise induced by data transitions on the front-side bus,
resulting in functional failures. Glitches can be seen on the various InClk signals, especially with
higher CPU clock multipliers (>10X FID), resulting in data corruption at the processor. This noise is
resultant of inductance in the bond wires of the AMD-761 system controller wirebond package.
Potential Effect on System. Typical functional failures result in a system hang.
Suggested Workaround. The motherboard should be designed to incorporate special low-pass filters on the
SDATAINCLK[3:0]# pins and must also adhere to specific board routing rules. The filter circuitry and
routing rules are specified in the latest revision of the motherboard reference design files (schematics,
gerbers, etc.) for the AMD-760™ chipset. For detailed background and solution information, refer to
the following application note:
Analysis of Crosstalk Noise on the System Bus INCLK Signals in the AMD-761 System Controller, order#
24748A.
Please contact your local AMD specialist for details.
Resolution Status. None.