Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (140399)	7/29/2001 6:36:10 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Dan, <But putting even two chips on such a bus results in contention for the memory bus.> Absolutely false. It doesn't matter whether you have a single multiprocessor bus or two P2P processor interfaces. They're all going to access one memory bus anyway, at least on Intel's and AMD's dual-CPU chipsets. <It's a simple bus that doesn't scale well for multiprocessor applications, but it does make it easy to add additional processors, however fast any incremental benefit may fade.> The performance scaling is almost double when you go from one to two processors on the Foster bus. That's good enough to match the scalability of the EV6 bus architecture. As for going past 2-way, well AMD isn't there yet so your point is moot. <Xeon is also limited to caching 12 locations for any given offset.> Please explain. I can't tell whether you are talking about the cache, the TLB, or something else. Tenchusatsu