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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (140400)	7/29/2001 7:02:39 PM
From: Dan3	Read Replies (3) \| Respond to of 186894

Re: They're all going to access one memory bus anyway Execpt when they're addressing video card memory, disk controllers, network cards, and other such devices that typically run under heavy load on a server. Xeon is also limited to caching 12 locations for any given offset. PIII can address 8 locations with the same LSB (Least Significant Bits), P4 can address 12 (4-way instructions + 8-way unified L1/L2). Athlon can address 2 with its L1 + 16 more with its exclusive L2.

To: Tenchusatsu who wrote (140400)	7/29/2001 7:38:13 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

Absolutely false. It doesn't matter whether you have a single multiprocessor bus or two P2P processor interfaces. They're all going to access one memory bus anyway, at least on Intel's and AMD's dual-CPU chipsets. A point I have tried to make in the past. P2P processor interfaces only move the bottleneck someplace else, they don't eliminate it. Plus they add significantly to pin count and add at least another clock to snoop cycles. You know all this but perhaps others don't, on Intel's shared bus, each processor can snoop transactions as they take place while on a P2P interface the processors can't see the other's cycles directly. This adds complexity and delays. With large L2 caches dramatically cutting down on bus traffic and the extremely high bandwidth available to Intel's P4 bus, the only advantage to AMD's P2P interface was they didn't have to design it. After years of stumbling just trying to get the simplest 2-way P2P chipset working, the disadvantages are obvious. EP