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To: Dan3 who wrote (140401)	7/29/2001 7:27:39 PM
From: Dan3	Respond to of 186894

The major contributors to the increase in real GDP in the second quarter were: Personal consumption expenditures (PCE), state and local government spending, and residential fixed investment [housing]. The contributions of these components were partly offset by decreases in equipment and software, in exports, and in nonresidential structures. bea.doc.gov A basic summary is that everything was flat or down except residential housing - which was up so much it carried the whole economy to a slight gain. If homebuyers ever lose their nerve this economy could implode overnight - and the AMD/Intel wars will become moot.

To: Dan3 who wrote (140401)	7/29/2001 11:08:34 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Dan, <Execpt when they're addressing video card memory, disk controllers, network cards, and other such devices that typically run under heavy load on a server.> You don't understand, as usual. Processor-to-I/O traffic makes up a very small percentage of overall chipset traffic. I/O devices typically access memory directly instead of relying on processors to provide them data. That's why in server chipsets, the memory channel typically supports more bandwidth than even the FSB. In the case of 760MP, AMD should have added a second DDR channel to balance out the bandwidth of the two EV6 interfaces. But I remember them saying that cost was a huge consideration in the 760MP design, which is why they stuck with one DDR channel. Guess you can't blame them, considering that the 760MP north bridge already has over 900 pins. <PIII can address 8 locations with the same LSB (Least Significant Bits), P4 can address 12 (4-way instructions + 8-way unified L1/L2). Athlon can address 2 with its L1 + 16 more with its exclusive L2.> And this is supposed to be a huge advantage, except on paper? Going from 8-way to 16-way isn't going to reduce cache thrashing that much. Not only that, but the latency of a higher-way cache is necessarily going to be higher. But hey, what do I know? All I do is server chipsets for a living. ;-) I can't argue with the superb results that AnandTech showed, but I can argue with AMDroids who are emboldened by those results and act like armchair experts on this subject. Tenchusatsu

To: Dan3 who wrote (140401)	7/30/2001 9:55:52 AM
From: dale_laroy	Respond to of 186894

Dan, get a clue. >Execpt when they're addressing video card memory, disk controllers, network cards, and other such devices that typically run under heavy load on a server.< These accesses are typically very low bandwidth, so low that the total bandwidth is probably less that the difference between the theoretical and actual bandwidth of PC133 SDRAM. Where the difference between a point to point bus and a shared bus would shine would be with dual channel DDR SDRAM memory, as is implemented with the nForce 420 chipset, or with a large L3 cache integrated into the controller, as is the case with Mamba. The nForce is not a DP chipset, so is largely irrelevant to the exchange. While Mamba will never see the light of day in the market. >PIII can address 8 locations with the same LSB (Least Significant Bits), P4 can address 12 (4-way instructions + 8-way unified L1/L2). Athlon can address 2 with its L1 + 16 more with its exclusive L2.< Associativity can have a major impact on server performance, up to about 8-way set associativity. The sixteen-way set associativity of Athlon is overkill in most applications, including servers. However, while a sixteen-way 256KB L2 cache may not be able to beat an eight-way 512KB L2 cache, it is significantly better than an eight-way 256KB L2 cache, especially with the Athlon L2 cache being exclusive. Far more important with regards to server performance is hardware prefetch, and with hardware prefetch sixteen-way set associativity could really shine, not so much because it increases the hit rate, but because it reduces the potential of normal cache thrashing resulting from the hardware prefetch itself.