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To: Tenchusatsu who wrote (140421)	7/30/2001 8:56:47 AM
From: Dan3	Read Replies (4) \| Respond to of 186894

Re: If the CPU is bursting data to a network controller, that means the PCI bus is being occupied by the NIC Sorry, not the best example. On an AMD system, if one CPU is writing to (or reading from) memory, the other CPU can be reading from memory, NIC, Disk controller, etc. Or, even with only a single CPU, there could be a concurrent DMA transfer between peripheral and memory while the CPU is is updating a different region in memory (there will be cases where there is contention for the same pages, but usually not). The FIFO buffers on each of the point-to-point busses will also allow for better utilization of the memory, I/O, and AGP busses. They act in a way that is similar to prefetch in a processor. The benefits are limited with a single DDR 2100 channel, but will scale nicely with DDR 2400, DDR 3200, etc. while P4 hits a wall with its single bus. Obviously, Athlon's bus will also take much more advantage of any dual channel configuration than P4's, too. Dan

To: Tenchusatsu who wrote (140421)	7/30/2001 1:54:53 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Ten - re: "I don't get it, Dan. Why do you continue to act like an expert when every point you make is grossly inaccurate? If the CPU is bursting data to a network controller, that means the PCI bus is being occupied by the NIC. The DMA transfer from disk controller to memory has to wait until the PCI bus is freed." Dan3 - Of Blow Hard Fame - is completely freaked out. His AMD stock has plummeted. His AMD CPU superiority has proven non-existent. AMD's new products are late - and are not helping AMD's business. AMD is projecting losses. Blow Hard Dan resorts to psychopathic lies to reinforce his image of AMD as a financial and technological leader - thereby shielding himself from the reality of AMD's collapse. Have pity on him - he may end up in Fuchi-Land some time soon - with Big Nurse. Paul