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To: wanna_bmw who wrote (51362)	8/16/2001 5:10:49 AM
From: pgerassi	Respond to of 275872

Wanna_bmw: Get off saying P4 has a 20 stage pipeline. P4 has a 28 stage pipeline with a bypass at 20 stages, if all code is in the trace cache and it is not modified. The former is not that often in most application code, but the later is quite rare. When comparing to a P3 you must compare the whole pipeline because at 20 stages P4 doesn't decode a thing and at 10 stages P3 does. If you compare back ends, you might compare 6 back end stages of P3 to the 20 backend stages of P4, but that just shows how much more miserable P4 is compared to P3 (P4 clock = 3.3 P3 clock) since the first 8 stages of P4 are the exact same as the first 4 stages of a P3, but only 1 pipeline wide on the P4 to 3 pipelines on the P3. Please compare pipelines doing the same tasks. Otherwise you are spreading false information and untruths. Pete

To: wanna_bmw who wrote (51362)	8/16/2001 8:57:18 AM
From: Dan3	Read Replies (2) \| Respond to of 275872

Re: Intel was able to get 2x increase by moving No, Intel went from 1GHZ to 1.5GHZ, with little or no increase in performance on most software. Motorola has said that SOI will let it produce 1+ GHZ CPUs with a 7 stage pipeline. Motorola had a 100% frequency increase from one week to the next with a very substantial performance increase (not that performance seems to matter to anyone these days). If you attribute the whole increase to SOI instead of pipeline change plus SOI (I wouldn't) you shouldn't be worried about Intel missing out on SOI, you should be terrified.

To: wanna_bmw who wrote (51362)	8/16/2001 9:17:52 AM
From: combjelly	Respond to of 275872

"You say that the combination of going from 5 to 7 pipeline stages, as well as going to SOI, allowed the G4 to go from 450MHz to 800MHz, right? That's a 78% increase. Intel was able to get 2x increase by moving from 10 pipeline stages in the Pentium III (with a maximum frequency of 1GHz) to 20 pipeline stages in the Pentium 4 (with a maximum of 2GHz), and using the exact same process. Of course, you would have made your point without exaggerating, but I guess old habits die hard, right?" As you should know, going from 5 to 7 pipeline stages in the same process should yield roughly a 40% increase in clock rate in a given process, assuming that transistor speed isn't your limitation or you have unbalanced your pipelines when you increased the stages. So if Motorola got a 78% increase total, then it is reasonable to expect that either they got some extra from re-balancing the pipeline or that SOI contributed quite a bit. Intel was able to get a 2x increase by doubling the number of pipeline stages on the P4, or about what you would expect.

To: wanna_bmw who wrote (51362)	8/16/2001 1:41:58 PM
From: TimF	Read Replies (1) \| Respond to of 275872

You say that the combination of going from 5 to 7 pipeline stages, as well as going to SOI, allowed the G4 to go from 450MHz to 800MHz, right? That's a 78% increase. Intel was able to get 2x increase by moving from 10 pipeline stages in the Pentium III (with a maximum frequency of 1GHz) to 20 pipeline stages in the Pentium 4 (with a maximum of 2GHz), and using the exact same process. Of course, you would have made your point without exaggerating, but I guess old habits die hard, right? 1 - Intel didn't get 2x the increase. 2x 78% is 156%. 1ghz PIII to 2ghz P4 is 100%. 2 - 5 stages to 7 is an increase of 40% in pipeline length. PIII to P4 is atleast 100% maybe more depending on how you measure it. Tim