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To: Tenchusatsu who wrote (142297)	8/28/2001 4:17:22 PM
From: fingolfen	Read Replies (2) \| Respond to of 186894

You're going psycho over a trivial matter, boy. Not sure I agree there, Tench. I agree that Pete is going Psycho... but I don't think it's over a trivial matter. He isn't, however, going psycho over the surface issue... AMD is in trouble. The Palomino core has clearly not clocked where AMD thought it would. The 1GHz Morgan, which still doesn't appear to be available in volume, runs at a 0.15V higher than the 900MHz Spitfire core. AMD's 0.13 micron process is MIA... Latest roadmaps show Q2'02. I want to pull a couple of interesting quotes from Anand's IDF review: ( anandtech.com ) "The 3.0GHz demo that was run involved the machine running Quake III Arena in a window while serving as a video management server for other computers in the same household. The digital video feeds encoded and sent out by the 3.0GHz system combined with the run of Quake III Arena kept the CPU utilization at 100%. The fact that the demo system did not crash while running at 3GHz with 100% utilization indicates that the yield on the CPU being used was very high." Translation: Intel using 0.13 micron can push the frequency on the P4 just as hard as they want to in order to maintain competitive advantage. Anand also says: "With a 512KB L2 cache, AMD will find it very difficult to compete with very high clock speeds with their current line of Athlon processors. Luckily for AMD, the Pentium 4 will only hit 2.2GHz this year with the Northwood core." ... at least according to current roadmaps. I'd expect the P4 2.2GHz release to be in solid volume, along with 512K P4's at lower speed grades to round out the high performance bins. Given the typical 1 year lag between "demo air cooled at IDF" and production, I would expect to see the 3.0GHz P4 in Q3 to very early Q4 next year... maybe the following roadmap? Q4'01: 2.2GHz Q1'02: 2.4-2.5GHz Q2'02: 2.6-2.7GYz Q3'02: 2.8-3.0GHz? Q4'02: 3.0GHz+? In short, what Pete is going ballistic over is the relegation of AMD to the value PC ranks once again. At release, the K7 gave AMD a big shot in the arm in that they finally had a true "tier 1" processor. Design wins and increased credibility followed. Market share inched up. The AMD supporters bought into the hype of AMD as the "giant killer." The nimble and pure Luke Skywalker defeating the vast monolithic evil galactic empire. As many said then, it makes good fiction, but reality is often quite different. Now, the P4 is starting to outpace the K7, and with the Palomino core nowhere in sight, the K7 becomes just another value processor. The price points for the K7 back-up that argument. Intel therefore "can't" have a 2.0GHz P4 or greater as it destroys that dream of the x86 market being 30%+ AMD... turn the page...

To: Tenchusatsu who wrote (142297)	8/28/2001 5:28:36 PM
From: Saturn V	Read Replies (1) \| Respond to of 186894

Tench, Ref- Jackson Technology. The Jackson technology is very interesting. It reminds me of IBM's dual processor on a chip, which was announced two years ago. This is two separate and complete CPU on a chip, but with a common L2. AMD's paper Sledgehammer sound very similar to the IBM approach. The Intel Jackson technology differs in using fewer transistors than the above two approaches, and appears more efficient. For example there is a common set of ALUs and FPUs shared between both threads. However they obviously have independent register sets( integer register file, floating point register file,program counters,flag registers and instruction registers). Does not each thread need an independent instruction decode, and instruction pipeline ? Are you in a position to comment about the implementation of Jackson ? The Jackson Technology and other multi threaded chips, benefit only those applications which been coded for multiple threads, and have small data set compared to the L2 size. If the L2 is small, each thread can cause eviction of the data needed by the other thread, leading to cash thrashing. So Intel is wisely first implementing it on large cache Xeons. The trend to multi threaded processors is inevitable because the CPU clock speed is continuing to outrun memory speed. This is causing cache sizes to explode. Even then cache misses are inevitable. So the second thread automatically starts executing when the other thread is stalled.