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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (52829)	8/28/2001 5:44:08 PM
From: Jim McMannis	Read Replies (1) \| Respond to of 275872

RE:"Basically, 2 reasons: a) they can, meaning Northwood with 512K L2 is a reasonable size, and actually since there are redundancies in L2 silicon, even the large silicon area doesn't reduce the yields as much as logic could b) I think there is an important feature of the L2 that has been only briefly touched on and that is multiplier. With multiplier of 20, each L2 miss will stall the CPU for 20 x the RAM latency CPU cycles, which in case of 10 bus cycle latency would be 200 CPU cycles. As the multiplier increases, so does the damaging effect of an L2 miss on the overall performance of the CPU." Rarely does Intel do something just because they can...they usually have to have a marketing reason. Since Mhz is the most important factor in marketing chips I don't see that much advantage to Intel by adding cache to desktop chips. Sure would be nice for users to have that extra cahe though. On the other hand wouldn't a desktop P4 with 512k cache cannibalize Intels hopes at higher ASPs on server chips with large caches AND hurt any transition to IA 64? With Intel there is always a "guidance" reason for how they make and price chips...no? Segmentation to maximize profits is the name of the game. Jim

To: Joe NYC who wrote (52829)	8/28/2001 5:46:33 PM
From: Elmer	Read Replies (2) \| Respond to of 275872

I think there is an important feature of the L2 that has been only briefly touched on and that is multiplier. With multiplier of 20, each L2 miss will stall the CPU for 20 x the RAM latency CPU cycles, which in case of 10 bus cycle latency would be 200 CPU cycles. As the multiplier increases, so does the damaging effect of an L2 miss on the overall performance of the CPU. Good points. I wonder how L2 size and memory latency will be looked at in light of Intel's new Jackson Technology announcement? The ability to switch to a different thread with no dead clocks will really change the equations. Latency is less of a penalty and bandwidth more of a benefit. That spells RamBus. EP