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To: Elmer who wrote (52839)	8/28/2001 6:06:19 PM
From: Joe NYC	Read Replies (3) \| Respond to of 275872

Elmer, I wonder how L2 size and memory latency will be looked at in light of Intel's new Jackson Technology announcement? The ability to switch to a different thread with no dead clocks will really change the equations. Latency is less of a penalty and bandwidth more of a benefit. That spells RamBus. Has there been any technical paper published on Jackson Technology? I find the subject intriguing theoretically, and I would like to get some idea of the implementation of how the switching between the threads happens. As far as bandwidth, I am not sure if any apps utilize anywhere close to the full bandwidth of P4, even with prefetching going wild, but Jackson Technology, once implemented will definitely increase the bandwidth demand, since one of the penalties offsetting benefits of Jackson Technology will be additional trashing of L2. Regarding Rambus, my suspicion is that it will expire before all of this happens. Joe

To: Elmer who wrote (52839)	8/29/2001 5:43:24 PM
From: fyodor_	Respond to of 275872

Elmer: The ability to switch to a different thread with no dead clocks will really change the equations. Latency is less of a penalty and bandwidth more of a benefit. That spells RamBus. If that spells Rambus, how come Intel has publicly stated that their "P4" server chipset will support, not Rambus, but DDR SDRAM? Maybe recent results showing that DDR SDRAM is actually able to come closer to its theoretical max bandwidth than DRDRAM (despite this being touted as one of the major advantages of DRDRAM over SDRAM) are actually true? -fyo