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To: Saturn V who wrote (53034)	8/29/2001 3:21:55 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Saturn V, Re: "You probably spent at least one hour composing the terribly long message and analysis. I almost got a headache trying to decipher your long winded post and the flawed analysis, and I am sure that several others must have had a similar experience." I think it's amusing that Pete spent all that time rebuking my response about cache architecture when I've already told him that I have him on ignore. I've found that arguing with him is absolutely useless. You'll only frustrate yourself, and he is able to roll with the strongest of punches. All of his rebuttals are based on fundamental flaws. I almost think that it's on purpose, most of the time. He thinks that he can fool people, but even the AMD thread pays him no mind. I would almost feel sorry for him except that he gets belligerent whenever anybody dispels his lies with actual facts. wanna_bmw

To: Saturn V who wrote (53034)	8/29/2001 3:53:54 PM
From: pgerassi	Respond to of 275872

Dear SaturnV: The fact that P4 has a 8K L1 data cache does not invalidate my results. Plugging in a 8K 2 way 64 byte cache line L1 into P4, just changes the clock cycles per L2 cache try to around 20 cycles. The L1 probably gets about a 80% cache hit rate since it is 1/4 the P3's L1 data cache. The L2 probably is at 95% or about a 1.65 frequency divisor. The 320K 20 way L2 (due to exclusivity) has about a 97% hit rate and a 40 cycle per L2 cache try or a about a 1.3 frequency divisor. That is about gives Athlon about a 30% advantage to P4. Increasing P4 to a 512K 8 way gives about a 96% cache hit or about a 1.55 frequency divisor or about 6% faster than the current cache. It still gives up 20% to Athlon. About what is found in typical code. It doesn't touch the L2 dicussions beyond that because the P4 is inclusive. Quadrupuling the cache miss rate to lose a L1 latency cycle (Intel's reasons for the small 8KB cache) shows up in a larger overall frequency divisor for P4. And it gets worse as clock speeds rise wrt memory speeds. It doesn't touch in any substantial way the rest of the post. Pete