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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: wanna_bmw who wrote (53170)	8/30/2001 1:40:58 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

wbmw, I think the reason why you will be unlikely to see such an occurrence has to do with the innate amount of instruction level parallelism that exists in even the most optimized code. Studies have found that increasing IPC past 3-4 instructions per second is nearly impossible, especially on x86 code, which has less ILP than other architectures. I guess you mean per cycle. Suppose Hammer improves IPC vs. Palomino, which has higher IPC than Thunderbird, which has higher IPC than P4, this could result that the performance levels of equally clocked Hammer chips would no longer be in the same ballpark as P4. It is within the realm of possibilities for IPC of Hammer to be 2x IPC of P4. Of course, when I talk about IPC, I mean IPC running productivity applications, code within OSs etc. This type of code is full of heavy dependencies, pointers, branches etc. Athlon and P6 do very will running this kind of code, P4 runs it poorly. P4 seems to excel on code with very little logic, few dependencies, simple repetitious code on huge quantity of data. On this type of code, I doubt IPC of Hammer will be significantly higher than P4. The possibilities for improving IPC would be things that reduce latencies, amount of time that CPU is stalled. The integrated Northbridge would contribute significantly, as well as some improvements in bandwidth, latency and size of L2. I don't know if Hammer family will have the same 64 bid datapath or more, but low latency and high bandwidth memory is what is needed for database servers. Another possibility for improved IPC would running code in full 64 bit (long mode I believe), which adds some general purpose registers, which could significantly improve IPC. Anyway, my point is that as long as Athlon and P4 performance are about the same, but Athlon has higher IPC and lower MHz, AMD will be have some trouble marketing their chips, unless they can explain it clearly. If the MHz and IPC diverge so that they are not in the same ballpark, it would be easier for AMD to make the point. Joe