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To: combjelly who wrote (53577)	9/1/2001 3:23:54 PM
From: milo_morai	Read Replies (1) \| Respond to of 275872

<font color=green>AMD Hammer Model 3500+ Near? By Zach Gusky Date: August 31, 2001 2.0 GHz AMD Hammer Chip Coming Soon? vanshardware.com PC Worlds take on it pcworld.com

To: combjelly who wrote (53577)	9/1/2001 3:37:23 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Combjelly, Re: "You mean that the P4 doesn't slow to half speed when the decode unit is used? When did they change that? " They haven't changed the behavior of the decoder. It's just that some people here have always been under the false impression that they have. The fact is that the Pentium 4 decoder decodes one instruction per clock into 1-4 uops. These all go into the trace cache, and form into a series of 6 uops called traces. Each of the uops in a trace are ordered in terms of program flow. On every other clock, the trace cache issues a trace into the processor back-end. This is where this thread is confused. The trace cache operates every other clock, not the decoder. However, since each trace is 6 uops long, this averages out to the same 3 Mops that the Athlon core can issue per clock. wanna_bmw

To: combjelly who wrote (53577)	9/1/2001 7:34:09 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 275872

Combjelly, <You mean that the P4 doesn't slow to half speed when the decode unit is used?> Remember when the Athlon's L2 cache was off-chip and running at 1/2 to 1/3 the speed of the processor core? Do you think the Athlon slowed down to 1/2 or 1/3 speed every time it accessed the L2 cache? How about on an L2 cache miss? Do you think modern processors slow down to the speed of the FSB when going to the chipset's north bridge? There is little difference in performance between a trace cache that provides x instructions per clock and one that provides 2x instructions every other clock. Of course, I doubt that's going to change the minds of 'Droids who think Intel's processor architects can't grasp basic concepts like Flynn's bottleneck. Tenchusatsu