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To: THE WATSONYOUTH who wrote (142950)	9/6/2001 1:03:20 PM
From: John Hull	Read Replies (2) \| Respond to of 186894

WY- fundamental assumption error here is that pricing on premium server CPUs has anything to do with cost of production. when intel first discussed Xeon pricing with CPQ/IBM and other major server players they told us we were pricing too low. this is the truth. have you checked recently what a major server OEM charges for incremental CPUs in a multi-CPU system. Intel parts are comparatively cheap. regards, jh

To: THE WATSONYOUTH who wrote (142950)	9/6/2001 1:29:40 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

TWY, Re: "I thought we were discussing various issues of POWER4 vs Itanium/McKinley. I NEVER once mentioned Xeon x86 anywhere in the discussion. Now you start in with Xeon x86. It seems you change the subject at will. You are a piece of work." Try to pay attention. It's not too hard. I gave the 900MHz Xeon as an example for what IBM is selling an Intel chip for, and compared it to what they are selling their own processors for. If you want, take what I said and remove the word "Xeon" and replace it with "Itanium". The point still stands. IBM has several processor lines that they research and develop. If Itanium replaces at least one, that will be an enormous money maker for IBM. Let's say MPR is correct, and it costs IBM $2500 to make a Power4 module, which they then sell for $100,000. That would be great to have a $97,500 profit on each module, but how many do you think they will sell per quarter? 1000? 2000? Not that it matters, since you also have to include the cost to design, debug, and develop the chip. Meanwhile, IBM will probably get a few thousand dollars of profit on each Itanium chip they sell. But a couple of years from now, Itanium will be selling orders of magnitude more than Power4 is selling, so it makes sense for them to carry that product line. And it isn't even the money they make on the processor itself, it's the margins they make on the entire Itanium system, whose volumes will be more of a money maker for IBM than any other of their processor lines. It doesn't matter that the margins per processor are much smaller. Yet when I confront you with this, you accuse me of changing subjects. I am not dodging the truth. You are. And you have some nerve of accusing me of changing the subject, anyway. If I recall, you previously responded to my post to Win Smith by changing the subject of the conversation, and that's what started this whole debate. I am merely getting the conversation back on topic. Message 16304628 wanna_bmw

To: THE WATSONYOUTH who wrote (142950)	9/6/2001 1:55:28 PM
From: fingolfen	Read Replies (1) \| Respond to of 186894

The majority of die space in Power4 is L2 cache. It has an aggressive redundancy scheme. Given that, the area for the two cores alone is probably less tha 200mm2 which is NOT larger than some of IBM's other processor lines and is in fact smaller than P4. What is the size of Itanium by the way???. POWER4 is on a .18um process and so is not more aggressive than other features in other processor lines. So, you are wrong AGAIN on both points. Even if you think it will yield only 10%, that would be perhaps 8 chips per wafer. That's $250/chip if the wafer costs $2K to process. So with a module that is estimated to cost $400, you could build two modules from one wafer (8 chips/16 cores) for $2800. That's $1400 per module at 10% yield. And... I know the yield is much higher than 10%. So, you are wrong once AGAIN. I have dodged no issues. You only dodge the truth. I really hate it when people attach the word "truth" onto a argument which is permeated with assumptions. It seems to me that there are too many variables here to call the position the "truth." I want to detail some of the assumptions and deal with them individually. First, I have not seen the die map for the Power4. what percentage of the die is L2 cache? Is that L2 cache tightly grouped like a coppermine, xeon, or tualatin, or is it subdivided into blocks? If the "majority" of the die space is L2 cache (50% or thereabouts), then yes, some yield can be regained by cache redundancy and fusing bad areas of the cache. It makes sense that they would put that scheme in place. So far so good. You then go on to state the the area for the two cores is probably <200mm2. Where do you obtain that number? Is that total die size, or just core size (i.e. is the total die size 200mm2 or >400mm2, since you've already contended that the L2 cache makes up the "majority" of the die)? You do realize that to have a functional die BOTH cores must work? If only one core works, the die is "bad" (unless, of course, IBM has included extra fusable cores on the die... which doesn't strike me as helping a lot in the long haul). The fact that two cores need to work to have a functional die will reduce yield. If the cores are 200mm2 PLUS L2 cache... then the die size is certainly going to approach Itanium. Not sure how big McKinley is, although Intel indicates it runs 200+MM transistors. You go on to assert that Power4 is on a .18u process and is therefore not more aggressive... That is a non sequitur. Aggressiveness is a function of the microprocessor design, not purely the process. Any manufacturing process will have critical design rules (gate pitch must be greater than X, contact width can't be less than Y, etc.). An "aggressive" design will try to gain performance and/or die-size by pushing those critical design rules to the absolute limit with great frequency, whereas a less aggressive design will only use critical design rules for the most vital speed paths and functional units. Any “aggressive” design is going to suffer yield fallout because natural process variation will push too many features beyond the design rules into areas in which the process is not stable. I would therefore submit that your assertion that the Power4 is not aggressive was based on an erroneous assumption, and without looking at the Power4 design and understanding the critical design rules for the IBM process… I honestly don’t think that they’re going to tell us either so we can make a solid fact-based analysis! Based on these assumptions you declare your opponent wrong… I’m not sure you have a strong case, and yelling isn’t going to strengthen it… You then go onto a yield and cost/die model. First, you are assuming 80 die per wafer as you indicate a 10% yield will result in 8 die per wafer. This means you must be using the a number close to 400mm2 as the overall die size. How are you modeling the packing as with a die that large many die will be partials? Without die size and shape, it’s impossible to get a solid die/wafer calculation… unless, of course, you know what steppers IBM is using and know their field size as this would clearly be a 1 die/field processor. Given a 400mm2 die size or greater, I honestly don’t think IBM will get a theoretical yield of 80 die/wafer. You then assume an IBM wafer costs $2K to produce. Where did you get this number? IBM has always been the hallmark of advanced technology… at any price. IBM is not a volume fabrication unit, they never have been. They are an “art” fab. They do it better and faster, but not always cheaper. I’m not saying that IBM’s 0.18 micron wafer cost isn’t $2K, but I’d like to see some sort of reference here. If they’re using SOI I honestly doubt they have a $2K wafer cost. You then go on to indicate a module cost based on die cost plus packaging (again, where did you get the overall cost of packaging and assembly?), and once again declare your opponent “wrong.” Again, there seems to be a LOT of assumption in here, so that’s a very strong statement… The crux of your argument is that one should compare IBM’s production cost and use it as a COG to compare to an IA-64 processor. Earlier in the message you accuse wanna of changing the subject, when in fact he was providing a relevant counterexample. The overall COG for IBM to produce a Power4 processor is NOT wafer cost + packaging cost. That neglects some very large contributor’s to IBM’s COG for a Power4: Microprocessor design (the design didn’t magically grow on the reticle plates), test, and validation (which can be very expensive). The parallel that wanna was trying to draw was that IBM uses Xeons for their x86 servers because IBM’s COG for design, development, test, validation, die, and package exceeds what Intel charges them. By extension the same may ultimately be true of IA-64 processors…