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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: andreas_wonisch who wrote (56999)	10/3/2001 9:23:18 AM
From: fyodor_	Read Replies (2) \| Respond to of 275872

Andreas: I hope they market it at twice the clock-speed then. E.g. a dual 2 GHz Hammer as 4 GHz. I hope they are marketed at a model#. AMD needs to find a scheme and stick with it. There is going to be a certain amount of skepticism in the beginning, but I don't see that it cannot be overcome relatively easily - given time. However, if AMD flip-flops on the scheme&#133 Have you read Hans' article? It's quite amazing and I have a hard time believing he got all his information from patents. -fyo

To: andreas_wonisch who wrote (56999)	10/3/2001 9:32:33 AM
From: fyodor_	Read Replies (1) \| Respond to of 275872

Integrated memory controller for Sledge, not Claw&#133 From the final portion of Hans' article: ClawHammer: 266 MHz EV6 bus replaced by 800 MHz Hyper-transport. A number of ClawHammer chipsets have now been placed on the roadmaps. These chipsets use Hyper Transport to communicate with ClawHammer at a presumable speed of 800 MHz and a total bandwidth of 6.4 Giga Byte/s. Three times that of the current 266 MHz EV6 bus. Hyper Transport is said to scale to 1.6 Giga Hertz and 12.8 Giga Byte/s. The Memory Controller is still integrated on the Chipsets with support for 266 and 333 MHz DDR SDRAM. One should hope that these chipsets support 128 bit busses to memory to take advantage of the higher bandwidth. SledgeHammer for 2 to 8 way multiprocessing A recently issued AMD Patent (6,275,905) on the name of Dirk Meyer and Jim Keller gives a possible system solution for an 8 way Sledge Hammer multiprocessing system. Such a system would contain four SledgeHammers each with two cores. Each SledgeHammer has its own memory controller on chip and three Hyper Transport busses. Two of these link to other SledgeHammers forming a rectangle with a SledgeHammer on each corner. The third bus interfaces each processor to its local I/O slots.