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To: Noel who wrote (144766)	10/5/2001 12:49:38 PM
From: Elmer	Read Replies (2) \| Respond to of 186894

Also, as WBW said I don't see how any other CPU would not have the same problem. One of the knocks on P4 has been that it has relatively poor branch prediction and with the deep pipeline the penalty is greater than a processor with a less deep pipeline and better BP. If this is true then perhaps the BP problem has been addressed on Northwood? A doubling of the cache doesn't hurt either. When you throw in Jackson Technology the processor has something else to work on while performing the fetch thus lessening the overall penalty. No? You'd almost think Intel had it figured out in the first place.... EP

To: Noel who wrote (144766)	10/6/2001 12:36:24 PM
From: Dan3	Read Replies (2) \| Respond to of 186894

Re: I don't see how any other CPU would not have the same problem. The long pipeline of P4 is more sensitive to cache misses than that of any other chip ever designed or proposed (at least, any I have heard of - I'd be interested to hear from anyone who has heard if there were any as bad or worse than P4). To partially compensate for that failing, aggressive prefetching and a long cacheline is used, which increases the demand for memory bus bandwidth. But all CPUs are raising their frequency faster than memory performance is increasing. Any CPU design, if the frequency is raised sufficiently high, will asymptotically approach a maximum performance level (for a given memory design). P4's long pipeline demands a 128 byte cacheline length and prefetching or performance is awful. The result, blatantly obvious when single channel SDRAM and dual channel RDRAM P4 systems are compared to SDRAM vs. DDR Athlon, is that P4 will hit a memory subsystem wall much sooner than other designs as CPU frequencies increase. P4's a dead end.