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To: dhellman who wrote (59475)	10/20/2001 8:18:46 PM
From: combjelly	Read Replies (2) \| Respond to of 275872

"What is taping out?" It means the design is finalized and ready for manufacture. The term originated when they made an actual tape, and that was then sent to the fab.

To: dhellman who wrote (59475)	10/21/2001 1:46:31 AM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

"What is taping out?" "Taping out" means that the whole design has consistent code that passes all RTL verification test cases, that the silicon area was allocated for each block of the design, that ground and power nets were designed, the whole design was mapped onto manufacturing libraries, linked to I/O pads/buffers, all routing was done within manufacturing restrictions, reasonable clock tree was generated that meet skew and load requirements, all custom blocks (memories, I/O drivers, PLLs/Dlls) and internal busses and top-level interconnect were placed and successfully linked together, that the post-placing and routing timing parameters were extracted back into logical design, that those back-annotated codes with timing constraints pass again all verification suits and meet timing goals, that a check has been done that no shorts has occurred between power rails in custom blocks, that every driver has adequate strength to drive corresponding net, that the power is properly delivered into power-hungry areas, that heat dissipation meets density goals, that ... what else did I forget?.. and the tool finally generates a set of files that allows to build a set of photomasks. This means the time to celebrate and nervously wait for first silicon to arrive for bring-up and real testing. Regards, - Ali

To: dhellman who wrote (59475)	10/21/2001 9:08:11 AM
From: Bill Jackson	Read Replies (1) \| Respond to of 275872

dhellman, CPUs are designed on suites of software tools, like an architect drawing a house. The architect tries to make sure he has no errors, no beams in the middle of the living room, is there enough of the right size pipe to operate the third floor bathrooms and swimming pools etc etc, and so they use these design suites to plan and lay out the entire CPU. Like the architect, they have many things to check, shorts, power, as Ali says it is a sea of details that go beyond the ability of a human to encompass, they just apply a number of design rules along with experienced engineers and at the end of the day out comes the layour data for all the masks for each level. These are virtual masks and then then go to a mask maker. These masks are made for .13 and use the latest in short wavelength interference mode design. Then they use this mask set to make 'first silicon', sometims it works and sometimes it does not, so they find out what is right/wrong and then change the masks to correct this and they keep going through this cycle until they get it right or throw it away and start over. Here are a few links to read about it. The first one is a PhD thesis and is a sea of details that will take you a while to go through, but it is worth the time as it gives a good education. It is ca 1997, so a bit out of date, but the principals used now are similar, at smaller feature sizes with extreme ultraviolet or xray tools etc. iue.tuwien.ac.at These other links are assorted stuff that is pertinent. there are enough links on them to keep you going for a week or two cymer.com matec.org e-insite.net micromagazine.com Bill