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To: fingolfen who wrote (146632)11/1/2001 5:57:40 PM
From: AK2004  Respond to of 186894
 
fingolfen
sounds like intel was more specific than I thought, thanks
Regards
-Albert



To: fingolfen who wrote (146632)11/1/2001 6:23:36 PM
From: Road Walker  Read Replies (1) | Respond to of 186894
 
f-golfen,

Good explanation.

It's obvious that the cost savings would be incremental over a time line, but the analysts didn't project that. I don't think that most of them grasp the scope of Intel's operations. They think that going to .13 and 300 will happen overnight, like introducing a new Burger King sandwich.

John



To: fingolfen who wrote (146632)11/1/2001 8:23:29 PM
From: maui_dude  Read Replies (2) | Respond to of 186894
 
fingolfen,

Thanks for the explanation. It probably explains only modest gains wrt the cost. But another way of looking at it is that Intel hasn't really gained much from P4/.13 transition (from a cost standpoint). Given a large P4 die size, .13 was a 'must', just to keep up (of course, it has a lot more room to continue to ramp up, but that doesn't help cost yet).

For a chip that is so much bigger than P3 and a new architecture, it should have been comparable in size (given their performance). I understand that Hyperthreading takes some real-estate and the extra area may be justified with the extra 30% performance gain. But until a working HT P4 chip is ready to ship, doesn't it make sense to ship P4 on .13 with a reduced die and improve the cost structure ?
Does anyone know if all these jackson technology layout is placed in one area to simply remove it and creating a new P4 stepping without major rework ? BTW, what percentage of the area is used up to enable HT in P4 ?

Maui.