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To: maui_dude who wrote (146658)11/2/2001 2:40:00 PM
From: Noel  Read Replies (2) | Respond to of 186894
 
Maui,

P4 die size reduction.

What makes you think removing 5-10% of transistors will reduce the die size? Most designs are metal limited not transistor limited.

Also, you will see a 25% cost gain from the transition to 0.13 micron as the P4 die size shrinks. But this comes from shrinking the design itself. Not due to a larger wafer.

What Intel is claiming is that they will eventually have a 30% lower cost on the same size die due to the switch to 300mm. So moving from 0.18 micron Willamette to 0.13 micron Northwood will give a great cost benefit and Intel will get a cost benefit again when the manufacturing of 0.13 micron is moved from 8 inch fabs to 12 inch fabs.

I don't think there has ever been a 25% cost gain just from process transition. The 25% cost gain comes because a shrunk part occupies 50% lesser area in a new process.

Ten, WBW, fingolfen, correct me if I am wrong on this one!