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To: jcholewa who wrote (62881)	11/8/2001 11:49:45 AM
From: wanna_bmw	Respond to of 275872

JC, Re: "I do not know enough about the trace cache yet. Why does it transfer every other clock?" I believe it's because the uop "Traces" were architected to be 6 uops long, so transferring 3 uops per clock wasn't an option. Meanwhile, transferring 6 uops every clock isn't worth while, since the execution resources couldn't even handle that many, which may just waste power. On the other hand, reducing it to every other clock while issuing 6 uops may have simplified the design (since a slower speed may have removed some of the speed path issues that would normally have existed), and that would be worth implementing. But other than these educated guesses, I don't know. wanna_bmw

To: jcholewa who wrote (62881)	11/8/2001 11:52:37 AM
From: kapkan4u	Read Replies (4) \| Respond to of 275872

<I do not know enough about the trace cache yet. Why does it transfer every other clock? Does it simply take two local cycles to move all the data to the next stage, or does the TC happen to have, as others might suggest, an 0.5x local clock multiplier and the "every other clock" thing is a reference to the MCLK?> Its the latter. Look here on page 1-9 developer.intel.com The decoder and the TC are in a box called front-end. They are both running at half of the MCLK. The front-end is probably as large as 30% of the chip, running at half the nominally quoted frequency. This is why Intel is hiding this information. It would be devastating to P4's marketing scams. Kap