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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (63194)	11/9/2001 11:42:16 AM
From: pgerassi	Read Replies (1) \| Respond to of 275872

Dear Fyo: Think about what it would mean if the primary thread was some small loop calculation loop and the second thread was an isosynchronous application requiring say 10% of CPU resources to keep going real time like DVD playback. The first would almost never have a L2 miss and the second can't keep up and misses a lot of frames, etc. Not a good situation. Second, much of the IPC gains will be lost over most situations and an optimized app may hog the CPU. No, the switch must be based over some small time. Every cycle or every few cycles with a stall causing an immediate switch. But, then we are back to needing more registers in the reorder pool. However, we do not need twice the number of registers in the pool. Given the current makeup of P4, I would estimate that for most situations, single digit percent increase would occur. Of course, Intel will find a few with increases in the low double digit % range and tout those. Most of the gains will come from increased L2 and later from FSB increases. Pete