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To: pgerassi who wrote (63220)11/9/2001 11:45:42 AM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Pete: Every cycle or every few cycles with a stall causing an immediate switch. But, then we are back to needing more registers in the reorder pool. However, we do not need twice the number of registers in the pool.

Intel seems to have indicated that at least part of the front-end will be "doubled" for SMT. More register resources is certainly not to be discounted. (I think more decoding resources and more trace cache are the two primary bottlenecks).

-fyo


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