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To: Petz who wrote (64119)	11/20/2001 1:23:28 PM
From: Ali Chen	Respond to of 275872

John, "more of a problem in SRAM transistors than in logic transistors" It is my understanding that a transistor is a transistor, and if it leaks, it leaks. If you look at Tulatin with 512k cache, it leaks about the same (10.2A) as regular 0.13 shrink of P-III with 256k (9.5A). "Secondly, doesn't high leakage result in greater sensitivity to noise problems, since it raises the "off" voltage level?" I don't believe so. There is no "off" level in ultra-low-voltage CMOS, there is about Vcc/2 switching point which does not change. - Ali

To: Petz who wrote (64119)	11/20/2001 2:08:44 PM
From: Pravin Kamdar	Read Replies (2) \| Respond to of 275872

John, is there any reason leakage can be more of a problem in SRAM transistors than in logic transistors? I'm not a memory designer, but I seem to remember from way back in my college days that SRAM must be refreshed every few milliseconds due to charge decay on the caps storing the positive memory bits. It seems that it would follow that leaky transistors would lead to higher refresh rates and higher current, and hence power, drain. Secondly, doesn't high leakage result in greater sensitivity to noise problems, since it raises the "off" voltage level? I'm not sure what you mean by leakage raising an "off" voltage level. In CMOS, the zero "off" voltage level leads to higher and higher channel leakage current (between source and drain) as the channel length decreases as processes are migrated to smaller feature sizes. You see, it is not only desirable from a power perspective to lower operating voltage with newer and smaller channel length technologies, but it is required to prevent "punch-through" between the source and drain. To explain this, the boundary between the sides and bottom of the source and drain diffusions and the bulk are reverse-biased diodes (commonly referred to as junctions). These diodes have a physical width associated with them -- part of which extends into the bulk, and part of which extends into the diffusion. The more voltage that is applied, the more the width of the reverse-biased junctions are extended. If too much voltage is applied, the edges of the junctions will extend towards each other under the gate until they touch, and short circuit the device. So, as the channel length is decreased, operating voltage must be decreased so that reverse-biased junctions of the source and drain do not punch-through. So, what does this have to do with leakage? Since the amount of voltage available to the gate is decreased (along with Vcc to avoid punch-through as feature size is decreased), the device must be designed with an impurity level under the gate that will give strong inversion and supply the high number of carriers to support high current flow between source and drain when the device is on. The only way to do this is to design the device so that it is approaching being on, even when it is off -- so that it can be strongly turned on with only a little gate voltage. So, since the device has to be designed so that it is not strongly off under zero gate voltage, high channel leakage current results. As for your question about noise -- I don't know. But I would guess that a high level of background leakage would lower sensitivities to all kinds of things. Pravin.