SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Pravin Kamdar who wrote (64122)11/20/2001 2:31:38 PM
From: tcmayRead Replies (4) | Respond to of 275872
 
"I'm not a memory designer, but I seem to remember from way back in my college days that SRAM must be refreshed every few milliseconds due to charge decay on the caps storing the positive memory bits. It seems that it would follow that leaky transistors would lead to higher refresh rates and higher current, and hence power, drain."

You are confusing DRAMs with SRAMs. Dynamic RAMs store a 1 or 0 on the storage cell capacitors (and not necessarily a "positive memory bit"--a full vs. empty well can be either a 1 or a 0, and may vary from one part of the array to another).

Static RAM consists of cross-coupled inverters, thus "locking" the cell into one of two positions, interpreted by the logic of the memory as a 1 or a 0.

Leakage currents affect various things. The claim that Intel's Mobile .13 processors are leaking 17 A at 1.3 volts is not supported. Such a leakage in sleep mode would imply the processor alone is disspating roughly 22 W.

The spec sheet I saw said 1.7 A, which is more plausible.

As to "problems" with noise, this would be mere speculation. Designers characterize such things all the time.

(Too bad you manibanners expelled Paul from your sandbox.)

--Tim May



To: Pravin Kamdar who wrote (64122)11/20/2001 3:02:13 PM
From: PetzRead Replies (1) | Respond to of 275872
 
Pravin, let me rephrase my second question:

Secondly, doesn't high leakage result in less noise immunity, since it raises the LOGIC 0 voltage level, and the LOGIC 1 level is limited by the Vcc?

For example if the transitor going to Vcc is 'off', but leaking a lot of current, and the transistor going to ground is 'on', the "logic 0" level will be higher than the case where the 'off' transistor is an open circuit.

Petz