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To: tcmay who wrote (64125)	11/20/2001 2:41:20 PM
From: Bill Jackson	Read Replies (2) \| Respond to of 275872

Tim, With higher leakage then the cache ram would need more frequent refresh and that would cut it's performance vis-a-vis the AMD cache. I am not sure, but I suspect the cache will be DRAM for space saving and not SRAM? is that correct? Or must it be SRAM for raw speed in the case of a CPU and thus needs no refresh? Paul would still be here if he was as well mannered as you are, Tim. Bill

To: tcmay who wrote (64125)	11/20/2001 2:56:17 PM
From: Petz	Respond to of 275872

<The spec sheet I saw said 1.7 A, which is more plausible.> Only at non-operational voltage levels. Take a closer look. The leakage increases exponentially with operating voltage as Ali pointed out. The claim that Intel's Mobile .13 processors are leaking 17 A at 1.3 volts IS supported at it's rated speed, which requires full Vcc. Petz

To: tcmay who wrote (64125)	11/20/2001 3:23:08 PM
From: Pravin Kamdar	Read Replies (1) \| Respond to of 275872

Tim, You are confusing DRAMs with SRAMs. Dynamic RAMs store a 1 or 0 on the storage cell capacitors (and not necessarily a "positive memory bit"--a full vs. empty well can be either a 1 or a 0, and may vary from one part of the array to another). Aaah, that rings a bell. But is cache memory used in processors the type that has to be refreshed? Hey, I never claimed to be a circuit designer (especially digital), even when I was designing them! Pravin.