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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Bill Jackson who wrote (64126)	11/20/2001 3:37:14 PM
From: combjelly	Read Replies (1) \| Respond to of 275872

" but I suspect the cache will be DRAM for space saving and not SRAM?" Not currently. DRAM has been used in the past, and might be used in the future for cache, but I don't know of anybody that is currently doing that. The problem is that DRAM is slower than SRAM, and speed is what is important in a cache. Now embedded DRAM would make a bang up L3 cache. Given that university group that uses the "floating body" effect in SOI to eliminate the capacitor, maybe AMD will think about a 4 or 8 meg. on-chip L3 cache for 90nm...

To: Bill Jackson who wrote (64126)	11/21/2001 1:18:39 AM
From: tcmay	Read Replies (2) \| Respond to of 275872

:Tim, With higher leakage then the cache ram would need more frequent refresh and that would cut it's performance vis-a-vis the AMD cache." First, we don't know the components of the "leakage" current. Could be substrate leakage, could be the current because the arrays and logic are not off, merely "sleeping." Could be other things. (CMOS in _theory_ has negligible standby current, but in _fact_ it has a component of current that increases linearly with speed. This is one reason the theoretical advantages of CMOS over NMOS have begun to narrow as switching rates have increased dramatically.) Second, nearly _any_ amount of "leakage" would have next to nil effect on "refresh," as refresh is not needed with SRAM. Third, all cache in today's (mainstream) processors is SRAM. There have been proposals for DRAM, but nothing has happened. (There are good reasons for this. SRAM has access times below 5 nsec, as you all know, while DRAM has mostly been stuck in the 50 nsec range. (I could be off on this by a few tens of nanoseconds...but I believe this is about right. For many years DRAM was around 60-100 nsec at the same time SRAM was around 10-15 nsec. The physics of latches and drive currents is quite different from the physics of charge in wells and sense amps. Though some SRAMs are now using sense amp technology increasingly....) "I am not sure, but I suspect the cache will be DRAM for space saving and not SRAM? is that correct? Or must it be SRAM for raw speed in the case of a CPU and thus needs no refresh?" As above, on-chip cache is almost uniformly fast SRAM. No refresh. "Paul would still be here if he was as well mannered as you are, Tim." Ha. That's a good one. The Coucil of Elders, the halfwits who run SI, is already threatening to suspend me if I say certain things. None of the eleborate charade of a "Vote to Ban Paul," just termination of my posting ability if this Council of Whatevers decides to. SI is a sewer, run by incompetents. They don't apply their rules consistently (witness all of the "Sh!t" and "F*ck you!" comments which skate by because of the asterisks and other euphemism characters. The Head of the Maniban spews his racist garbage against Israel and then freaks out when he is called on it. Infospace should pull the plug on this abortion. --Tim May