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To: Bill Jackson who wrote (64199)	11/21/2001 12:22:59 PM
From: tcmay	Read Replies (1) \| Respond to of 275872

"Tim, Well, I was aware of the need for SRAM in the highest speed cache, but I had hoped that the more compact DRAM would be useable in the L3 to allow more to be on the die. Too bad it is all SRM as that does indeed limit CPU makers. As for speed, it is true that the SRAM is indeed faster. I am not sure of the tech reasons that limit DRAM, I suspect some balance between the time needed to charge those capacitors and the time before they leak away has something to do with it. If you make them charge faster, then they leak away faster and you need more frequent refresh.." No, the refresh characteristics not linked in this way. There _is_ an issue that DRAMs are ordinarily _expected_ to be at or near room temperature, maybe up to 50 C, and that a DRAM array on a P4 or similar chip might be at 80C or higher. Designers would need to take this into account. But it's not the main reason DRAM is not integrated into CPUs. I outlined many of the reasons. To understand the issues, one really just has to spend an hour or so (maybe more...) figuring out how SRAMs and DRAMs work. As with learning anything, a couple of approaches may be needed. For example, at the most basic level, think of SRAMs vs. DRAMs this way: -- with DRAMs, think of a bunch of guys storing water in full or empty buckets. When a bit is queried (addressed), the guy dumps his full or empty bucket into a pipe and the water flows to a place where someone looks at it and says "I think it was full" or "I think it was empty." -- with SRAMs, think of some relays or latches locked into one of two states. When queried (addressed), current flows out of the latch in one of two distinct places. So with DRAMs a bucket of water is being transferred and measured, while with SRAMs the output is seen more directly. (This is just a first pass. SRAMs are more than just crude latches, and designers get trickier and trickier as the years have passed, finding ways to speed up access with even sense amp sorts of tricks. And as geometries get very small, even "static" logic starts to look a little bit dynamic...) SRAMs, including CMOS SRAMs, are easily integrated onto CPU die. In fact, SRAMs are often the "process driver" for CPUs, the mass production technology used to debug or drive a technology. When Intel withdrew from the DRAM and mainstream SRAM market in 1985-6, many of us worried that the 386 would have no good process driver. Well, turned out that Intel continued to make some SRAMs on the process, and used them internally. And other debug techniques were devised. Intel's yields on CPU processes climbed to unexpected new heights. I was shocked to hear how good the yields were (how low the defect density was, that is). But spending an hour or two reading some good articles on how SRAMs work and how DRAMs work is essential. Without that, too many opportunities for misunderstanding of the basic physics. --Tim May