To: AK2004 who wrote (149822 ) 11/27/2001 12:39:08 PM From: fingolfen Read Replies (3) | Respond to of 186894 But there are limits to how far Intel will go. The company still opposes the use of silicon-on-insulator technology as a way to eke out more performance. Bohr said SOI's advantage will erode with each new process technology spin. This strategy contrasts with that of IBM Microelectronics, which will introduce both a conventional bulk silicon process as well as a high-performance SOI-based process at the 0.13-micron generation. While SOI has some performance advantages, Bohr said there are still problems related to wafer quality and an assumed loss of transistor switching speeds because of variations in the charge of the process' "floating body." Meanwhile, junction capacitance, which is alleviated in SOI, is becoming less of a problem with each process technology generation, Bohr said. I understand the problem you're having here Albert... I've actually looked at the entire Intel presentation based on the new transistor, and it is a new transistor design. All of the arguments made previously deal with SOI as it is produced and utilized today. The system Intel detailed is nothing like anything anyone produces today. The primary reasons for moving to an SOI solution like Intel's are for off state leakage issues, not junction capacitance issues. Conventional SOI is essentially a normal CMOS transistor floating over a buried insulator layer. The source and drain regions of the transistor do not reach down to the oxide. The Intel design differs in one important facet, the source drain regions and channel are very thin, and the S/D regions actually contact the oxide layer. This effectively eliminates the off-state leakage. Also remember, that the "thin SOI" was only one of the innovations presented. The "high-k gate" was also extremely interesting and shows a great deal of promise in moving away from the very thin, and therefore leaky, SiO2 gates currently in use in the industry.