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Technology Stocks : SOITEC, Silicon-On-Insulator TEChnologies -- Ignore unavailable to you. Want to Upgrade?

To: The Ox who wrote (50)	12/4/2001 9:12:52 PM
From: The Ox	Read Replies (1) \| Respond to of 83

SOI wafers called challenging, but not out of reach By Ron Wilson Integrated System Design (12/04/01, 3:36 p.m. EST) SAN MATEO, Calif. — This year's International Electron Devices Meeting will hear a larger number of papers about silicon-on-insulator technology than any previous session of this IEEE conference. In addition to the widely reported Intel Corp. papers — in which that company appears to reverse its skepticism of SOI technology and embrace fully depleted transistors for the future — IBM Corp. will present a record number of its own papers on SOI. "We will be describing not our first venture into SOI, but the results of work on our fourth generation of SOI designs," said IBM fellow Bijon Davari, who is vice president of technology and emerging products . "We will also lay out the landscape for the technologies we intend to build upon the SOI platform, from silicon germanium transistors to embedded DRAM." Underlying all of these papers, to be presented at the IEDM in Washington this week, is a highly pertinent question: Can the industry supply the wafers necessary for such advanced designs? Creating an SOI wafer is not the problem. Two viable processes — bonded wafers and Simox — exist for producing a wafer with a film of epitaxial silicon lying on a layer of oxide. But in their search for higher-performance transistors, semiconductor manufacturers are demanding thinner and thinner oxide films. IBM intends to be in production by the end of 2002 with a 0.13-micron process that uses 50-nanometer-thick silicon on top of the oxide, Davari said. The transistors Intel described to the press last week required an epitaxial film only 30 nm thick. To create an epitaxial layer this thin across a 200-mm or 300-mm wafer with sufficient uniformity and purity to produce reliable transistors sounds like a near impossibility. "Lattice quality is a major issue for silicon layers this thin," said Intel technology analyst Rob Willoner. "The suppliers have a lot of work ahead. Frankly, it is a challenge for the industry infrastructure, and one of the reasons for publishing our work at this time." But IBM's Davari is more positive on the subject. "Thirty-nanometer films are a ways out yet, but not that far out," he said. "We expect to have enough wafers for our 50-nm requirements in 2002, and we will be moving to films even thinner than 30 nm after that. Producing the wafers requires very careful implantation, oxidation and annealing, but it is being done." Wafer suppliers agreed. "In July of this year we already announced a product for these fully depleted processes, with silicon as thin as 30 nm," said Soitec president Andre Auberton-Herve. "We are getting very nice uniformity — our 6-sigma uniformity now is only 1.5 nm." Auberton-Herve explained that with the hydrogen-implant technology Soitec uses in its bonded-wafer process, it was possible to control film thickness to within a few atomic layers. He did allow that the process was not without its tricks. Nevertheless, "it was necessary to start producing these wafers to support the research programs now going on in the industry," he said. The process should have a good life, because as device researchers require thinner films, the 30-nm film can be reduced by additional — unspecified — processing steps. A spokesman for Canon agreed with Auberton-Herve's claim, stating that 30-nm films were within the reach of existing wafer-manufacturing technology. With wafers a solvable problem, and with SOI clearly on the road map for many of the major players in the performance-critical segment of the IC industry, the next major hurdle may be characterizing the SOI transistors and producing device models that today's tool chains can use. That also, according to Davari, will lie somewhere between triviality and impossibility. Ron Wilson is editorial director of Integrated System Design, a sister publication of EE Times.

To: The Ox who wrote (50)	12/4/2001 10:01:46 PM
From: kinkblot	Read Replies (1) \| Respond to of 83

Voids, nothingness, etc. While I was snoozing through Existentialism, these guys were obviously paying attention. <g> There is no limitation on the layout. Unlike SOI, we can put SON wherever we like on the wafer. It means we can keep the benefit of SON and keep our embedded DRAM. This will prove very useful for our future SoC chips. I see, they'll have their cake and eat it, too. Could be a competitive advantage. I thought Intel might be doing a localized insulator when I first heard of their announcement, but it turns out they'll start with an entire SOI wafer just like the 'regular' SOI guys. Fun with gaps in mems: focus.aps.org