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To: Timothy Liu who wrote (151239)	12/5/2001 6:34:25 PM
From: wanna_bmw	Respond to of 186894

Tim, I believe that the confusion that most technical sites had initially was what they believed was a trace cache issue rate of 3 uops per CPU nominal clock; later (and I don't remember where), it was revealed that the real issue rate was 6 uops on every other clock. It may be a fact that much of the trace cache runs at the full clock, but at least the issue logic runs at the half clock. wbmw

To: Timothy Liu who wrote (151239)	12/5/2001 6:35:02 PM
From: Joe NYC	Read Replies (2) \| Respond to of 186894

Tim, The fact that Trace Cache runs at half speed has been documented. I don't have the link handy. It was something about delivering some number of uops every other clock cycle. Your link is a review by someone, who does not have any better clue than you and I. Your second link about P4 decoding 1 instruction each clock cycle, I don't think anybody disagrees. But the point is, that the clock runs at half of the marketing speed. It's like saying that P4 bus delivers data 4 times per clock cycle. But the clock runs at 100 MHz. Joe