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To: Ali Chen who wrote (151267)	12/5/2001 10:14:03 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Ali, <Which, technically speaking, means that no bulk cache can run above that physical limit on any 0.18 Intel device> I'm quite sure Intel has made gains since 1999 (the year that IEEE paper was published). ;-) Tenchusatsu

To: Ali Chen who wrote (151267)	12/5/2001 11:54:43 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Ail - Re: "No problem, no one is perfect..." Except you - you're a perfect a$$hole.

To: Ali Chen who wrote (151267)	12/6/2001 12:05:28 AM
From: wanna_bmw	Respond to of 186894

Grinch, Re: "What does it tell you if the main pipe can consume 6 uOps per clock (which is 2GHz current maximum), but the Trace Cache "imposes" 1/2 limit to it? Now, if Intel designers have decided to "impose" this limit, why would anyone to make a decoder that would run twice as fast as the cache can consume? Where the result would be stored in this case?" I do agree with you about the cache running at half speed, but I don't see where the bottleneck lies that you are talking about. Instructions typically decode into 1-3uops each (there are much rarer instructions that decode into many more, but you aren't likely to see these even 1% of the time). Therefore, a trace cache that issues 6 uops every other clock cycle (or averaged to be 3uops per clock cycle) fits quite well with one decoder running full speed. Also, the limit that is mentioned is a "dispatch" limit - not a "consumption" limit. There is a difference. wbmw