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To: Tenchusatsu who wrote (151418)	12/6/2001 6:43:42 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Tenchusatsu, Re: "I can almost guarantee that a 1.4 GHz P4 has a shorter latency (in terms of # of clock cycles) than a 2.0 GHz P4." I don't disagree with your conclusion, but just where did you come up with this? wbmw

To: Tenchusatsu who wrote (151418)	12/6/2001 6:52:57 PM
From: Joe NYC	Read Replies (1) \| Respond to of 186894

Tenchusatsu, Uh, no. I can almost guarantee that a 1.4 GHz P4 has a shorter latency (in terms of # of clock cycles) than a 2.0 GHz P4. But the bandwidth per clock is constant. How can this be? Can you explain? These are identical processors. The L2 latency depends on the speed of the logic and it is completely in the are of the chip which runs at frequency set by the multiplier. You set multiplier to 14 on one, 20 to another. How can the latency be any different in terms of clock cycles? Am I missing something? Even if the decoders ran at half-speed, I don't think that would make a difference in performance as long as the decoders did double the work every other main clock. In theory, you should be able to fetch and decode more instructions per clock than you can execute. So if you're going to architect a split-clock processor, it makes sense to speed up just the execution side of the pipeline instead of the whole processor. Theoretically yes, you can have 2 decoders. But P4 has only one that can process one instruction per cycle. That's what the spec says. Joe