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To: Elmer who wrote (152139)	12/12/2001 9:21:47 AM
From: combjelly	Read Replies (2) \| Respond to of 186894

"To achieve this AMD would have to produce a large die with large cache." Not necessarily. Big caches are needed to reduce memory contention in a shared memory system. They are not as necessary in a point to point memory system like AMD uses. Yeah, there are some programs that benefit from a very large cache and there is a performance advantage there, but it isn't a given. As far as the dearth of customers for the Hammer, we will see once it starts to ship. There is a lot that can happen over the next year or so. Sample silicon will likely be available in Q102 and then we can talk.