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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: whortso who wrote (66249)	12/25/2001 11:56:49 AM
From: Dan3	Read Replies (1) \| Respond to of 275872

Re: I've been looking around for a link that shows the size of Intel's fabs Message 16829926

To: whortso who wrote (66249)	12/27/2001 10:34:47 AM
From: fyodor_	Read Replies (1) \| Respond to of 275872

whortso: I think you [pete] just confirmed his case for him [elmer]. Except that the calculation assumed 100% ramp of Dresden, which is not the case and an, arguable number of chips out of Dresden. Also, the estimate (clearly labeled absolute minimum, btw) did not include edge loss! Asumming Dresden to be 2/3 ramped (last Q) and keeping the 4M die, one can arrive at a better approximation. However, you are still ignoring a huge factor: the 5000wpw listed as the max capacity of Fab30 is an all-inclusive, theoretical maximum! In practice, this max is never attained due to a variety of issues… new stepping runs, process tweaks, machine downtime etc. All of which do not reflect the yield, which is what Elmer claims is extremely poor. (These factors should be taken into consideration for both AMD and Intel calculations, of course.) Additionally, and likely very significant, AMD doesn't use special Development Fabs (which Intel does). All of AMD's process development takes place in Fab30 and certainly costs wafers! That SOI process isn't just going to pop into existence all on its own one day ;-). How many wafers does the process development cost? Well, considering that Intel uses an entire fab (albeit likely not fully ramped) for its development, probably a significant amount. Just for the heck of it, lets assume 20% of the fully ramped fab (this is a major WAG). To do the calculation, we also need an estimate of edge loss. 15% has been repeated many times on the semi threads of SI, but I don't know if this is a fair estimate. I've also noted a formula (Tench or Elmer, maybe?) for calculating (an estimate of) this property (possibly includes "cutting waste" as well): (2@PIr)/@SQRT(2die area) This formula gives a somewhat higher loss, but let's stick with the lower number of 15% for now. That brings us to: (5,0002/3)-1,000 = 2,333 wpw 4,000,000/(2,33313) = 132 good die per wafer 85% 31416mm² = 26704mm² effective wafer area Using 128mm² die size results in a yield estimate of 63%, using the lower estimate of edge loss, assuming 100% uptime for the equipment etc. Of course, there are so many WAGs in this that you could well argue the meaning(lessness) of this yield estimate. This is why I've argued many times that we just don't have anywhere near enough information for even an educated guess, let alone reasonable estimate! I'd consider the 63% little more than a W.A.G. -fyo