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To: Elmer who wrote (66566)	12/30/2001 1:06:47 AM
From: Dan3	Read Replies (1) \| Respond to of 275872

Re: you don't have to add 2+2 and get 4 to prove the device works correctly. If you can more easily show the gates that do the addition are defect free then you have accomplished the same thing. LOL! So, we finally find out how Intel managed to qualify 3 RIMM reference designs, ship the MTH, ship the 1.13GHZ PIII, ship Itanium workstation chips and ship Itanium server chips without knowing that they didn't always come up with 4 as the sum of 2 + 2.

To: Elmer who wrote (66566)	12/30/2001 8:25:27 AM
From: Bill Jackson	Read Replies (1) \| Respond to of 275872

Elmer, You say that modern chips are so complex that a thorough test would take quite a while, so they build in section test systems and as long as all sections work OK and the pathways between them are OK it can replace comprehensive testing? Sounds valid, probably done on the die before socketing, followed by a go/nogo test after that? I can see that with 5000 WPW with 200 or so CPus/wafer that you would nead enormous parallelism of testers to keep up. If the tests took one hour you would need 6000 or for the 100/minute rate of production. Even at a minute per test you would need 100. So that is one of the bottle necks. I wonder if testing is a P-4 bottleneck? Are there a sea of untested P-4 in huge wafer parking lots on the shop floor? Bill