SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: milo_morai who wrote (157044)1/27/2002 7:45:12 PM
From: Paul Engel  Respond to of 186894
 
Ban Ban MindBlo - re: "My point was Latency becomes more important as CPU IPC increases"

Looks like the Hamster is about 18 months latent.



To: milo_morai who wrote (157044)1/27/2002 10:01:15 PM
From: wanna_bmw  Read Replies (2) | Respond to of 186894
 
Milo, Re: "My point was Latency becomes more important as CPU IPC increases. If you cannot get the data to the CPU fast enough you do not scale linearly. Of course having more Cache lines will reduce latency to a degree as well."

Neither latency nor bandwidth by themselves is relevant when talking about getting data to the CPU. Throughput, which is the product of bandwidth and latency, is. The thing with bandwidth is that many things can be done to increase it, including increasing the memory clock frequency, increasing the data bus width, and adding additional strobes to latch data at multiple places during each clock. Latency, however, is not so easily improved. As clock frequencies increase, memory timing becomes more difficult. Getting equal latencies becomes hard enough, while reducing latency becomes even more difficult. AMD is buying themselves a one time latency benefit by integrating the memory controller. This will allow the system to be without the delay due to a Northbridge; however, memory latencies will be the same. While overall latency is decreased, AMD's solution does nothing about the latency from the CPU to main memory. Meanwhile, integrating the controller does limit the system memory options to what the controller will support. I don't see this being a huge deal for AMD, but it might affect them later in the future.

Re: "I'm sure INTC is looking to follow AMD's lead in integrating the memory controller."

Milo, I see some markets where an integrated memory controller would be beneficial. One of them is the high end server market, where memory standards typically stabilize with one standard for a long period of time. Thus, the integrated controller wouldn't be too much of a factor. Another market would be the very low end, such as where Intel aimed Timna. Since it's ok in that market to be behind in memory technology, I can't imagine that integrating the controller would have too many side effects. Therefore, I can see Intel launching a new kind of Timna, or even a high end server product, which may include an integrated memory controller. However, AMD is aiming Hammer at low end servers, and in the desktop, and in those markets, I see an integrated memory controller as a mistake.

wbmw