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To: wanna_bmw who wrote (157097)1/28/2002 1:16:23 AM
From: milo_morai  Read Replies (1) | Respond to of 186894
 
Wanna you're looking at the small picture and I'm looking at the large picture. That is only a small improvement. Integrating the memory controller and improving the cache hits is the best place to find large performance gains. And this is done by improving the latency so the data is always there for the next Instruction.

M.



To: wanna_bmw who wrote (157097)1/28/2002 1:45:28 AM
From: milo_morai  Respond to of 186894
 
Wanna some URL's for you on RLDRAM www-cad.eecs.berkeley.edu

infineon.com

And here's a URL that is similiar to what hammer is going to do iram.cs.berkeley.edu

And one on Latency peripherals.about.com


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