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To: wanna_bmw who wrote (157383)1/30/2002 10:28:48 PM
From: Elmer  Read Replies (1) | Respond to of 186894
 
AMD has been saying that for a long time. It certainly would be an enormous accomplishment, if they can. 12.5M CPUs per quarter on 5000 WSPW means roughly 192 good die per wafer. Since a 200mm wafer can fit 343 total 80mm^2 die, 192 good die works out to 56% yield (which might break down to ~60% die yield and line yield in the lower 90's). These are not improbable numbers.

Very interesting!

192 good die per wafer from a 80mm die would actually be terrible yield. Not just bad yield but terrible. Using that same defect density, a die the size of today's Athlon, 129mm2, would produce about 89 GDPW. Allowing for 4500 wafers per week during Q4, AMD should have been able to produce 89*4500*13=5206500 good die with the same terrible defect density. Allowing for backend yield and line yield we are very close to 4.5 million Athlons produced in Q4. So AMD's own projections for future yields are in complete agreement with the terrible yield theory I and Paul have presented here.

Thanks AMD for confirming what we already knew.

EP



To: wanna_bmw who wrote (157383)1/30/2002 10:58:42 PM
From: milo_morai  Read Replies (3) | Respond to of 186894
 
Did you look at the slide? GDPW veracast.com