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To: dale_laroy who wrote (71915)2/19/2002 1:01:58 AM
From: Joe NYCRead Replies (2) | Respond to of 275872
 
Dale,

I would guess improved Branch History Table and 128-bit transfers between cache levels.

Why 128-bit? It is 64-bit now, Intel's is 256-bit. If AMD were to go through the effort, why not go to 256-bit?

I seem to recall from previous discussions, that there was a bottleneck in moving data from L1 to L2 (not just the other way around, which would also benefit from increase width.

Joe



To: dale_laroy who wrote (71915)2/19/2002 8:46:37 AM
From: fyodor_Respond to of 275872
 
Dale: I would guess improved Branch History Table and 128-bit transfers between cache levels.

Is the current 64bit implementation bidirectional?

Would it make sense to do 2 unidirectional instead? (lower latency, simpler design).

-fyo


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