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To: AK2004 who wrote (72917)	3/1/2002 10:33:19 PM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

My post on Aces's Hardware: > > It looks like there will be 3 types of Hammer: > > - Clawhammer - Q4 2002 - 1HT, 1 DDR > > - Clawhammer DP - Q2 2003 - 3 HT, 1 DDR > > - Sledgehammer MP - Q2 2003 - 3 HT, 2 DDR > > This looks reasonable to me, except that the Clawhammer DP > will have 2 HT, not 3 (!) I would think so too, but for some reason AMD's MPF presentation (page 41) shows a dual configuration, and CPU with 3 HT channels, 1 channel on each unused. BTW, the my list of 3 possible Hammer versions is not meant to be a comment on pin outs, just CPU implementations. I think some of the connections (like 2nd DDR channel) and even 2nd and 3rd HT channel will be included in the base 756 socket, but their use will be optional. > > The most optimistic scenario I can think of is this: > > - Clawhammer - Q4 2002 - 1HT, 2 DDR, 1 core > > - Clawhammer DP - Q2 2003 - 3 HT, 2 DDR, 1 core > > - Sledgehammer MP - Q2 2003 - 3 HT, 2 DDR, 2 cores > > It is interesting. apparently 81 of the 186 new pins are most > likely power pins only, as they occupy the 9x9 center pin > matrix of the CPU which isn't reachable by motherboard traces, > only leaving 105 pins for the extra features on Hammer - > namely more HT links and 1 more DDR link. Hence some people > think that Clawhammer has a memory controller that can do > 128-bit DDR already, but it is just limited at the moment > because it is A0 silicon, or because it is a future option. > Then the extra HT link will fit in the pin space allotted. It may be entirely possible to fit all the necessary pins for 2 DDR and 3 HT channels into the budget of 754 clawhammer. If Hans is right about the need for 126 pins for 1 DDR channel, and let's take my pincount for 16 bit HT, not Hans's (since mine is more conservative), we get: 1st DDR channel: 126 pins 2nd DDR channel) 126 pins (optional ?) 1st HT channel: 84 pins (without ground) 2nd HT channel: 84 pins 3nd HT channel: 84 pins -------------------------- Total 504 pins Other 250 pins -------------------------- Socket 754 pins > It would be a shame if you couldn't use a standard Clawhammer > in a dual processor box though, the DP version should really > have another name (between Claw and Sledge)Hammer. I think it may be a question of implementing the coherent HT or not. A system with coherent HT implemented may have to deal with performance limiting overhead. Not implementing it may involve just hard wiring certain paths, simplifying and speeding up some paths, or even excluding some of the logic that deals with routing and switching HT pockets. Bottom line, higher performance. If there are different versions of silicon for the Crossbar, it would be the high performance simplified 1 channel HT version, and one with full functionality of 3 cHT links. As far as what kind of CPUs will be implemented, I bet there will definitely be one with single HT link, and a version with 3 HT links. The 2 HT link version would be just excessive segmentation (by disabling the 3rd link). As far as inability of Clawhammer to be used in dual version, it is on the roadmap (why else would there be a Clawhammer DP version on the roadmap, if regular Clawhammer can be DP). I don't think it is a shame, or anything like that, since IMO, there will be some performance boost for the single processor, and as of today, some 99% of AMD processors are being used in single processor configuration. IMO, if anything is a shame, it is if the first version of Clawhammer lacks ability to use 2 DDR channels. Joe

To: AK2004 who wrote (72917)	3/1/2002 11:53:47 PM
From: kapkan4u	Read Replies (3) \| Respond to of 275872

<I read it as amd saying 3400+ and ssb guessing that that would mean that the actual frequency would be 2.8GHz. I guess ssb used athlon-type linear conversion rule to get to actual frequency.> Thats how I read it too. Clueless JJ strikes out again. Kap

To: AK2004 who wrote (72917)	3/2/2002 12:44:09 AM
From: hmaly	Read Replies (1) \| Respond to of 275872

Albert Re...I do not believe that he made that statement. I read it as amd saying 3400+ and ssb guessing that that would mean that the actual frequency would be 2.8GHz. I guess ssb used athlon-type linear conversion rule to get to actual frequency.<<<<< It doesn't make as much sense that way. If you read it this way The company provided the latest processor roadmap, with a 2.8GHz (our estimate; their claim is a 3.4GHz P4 equivalent) part shipping by the yr. 2002. The product is currently sampling with key customers.<<<<< and leave the phrase regarding Hammer out, it makes more sense. Secondly the next sentence; The product is currently sampling with key customers.<<<<< is more likely to mean TBred as TBred is currently sampling in its final version to AMD's key customers. Hammer, AFAIK is only sampling to a few OEMs in its AO version; not the final version most customers would likely see. So I think he is referencing TBred; which by the way is slated to come out in a 2800+ version in q4.