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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: pgerassi who wrote (73888)	3/7/2002 1:40:41 PM
From: jcholewa	Read Replies (2) \| Respond to of 275872

> Paul DeMonde has been an Intel booster. > It is just like him to denigrate AMD successes.   You don't know Paul. He bashed Merced mercilessly and was the first person to (in an article) detail IA-64 as a parallel to Intel's previous server architecture failures (the i860, not to be confused with the chipset of the same name).   He came down hard on Rambus. It was because of him that people had ammunition when they needed to fight various claims made by Rambus fans. He explained, in detail, the problems with heat, latency, and so forth, of the memory.   He happens to think that Intel made the right choice in setting aside pipe stages for wire delays, an act which may allow for greater rampability with process shrinks. This could easily be a correct assumption.   It is really, really unfair to make false statements about Paul. Paul likes AMD and he likes the Athlon. Maybe he doesn't like the changes that are being made for the Hammer (I don't get that impression from what I've seen him write, but you have, apparently). That doesn't mean he hates AMD and has some sort of agenda for Intel!       -JC

To: pgerassi who wrote (73888)	3/7/2002 1:43:19 PM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

>Athlon has 10 stages and runs just fine to 1.8GHz and now he thinks that Clawhammer needs 18 stages to get to 1.8GHz. He is soundly mistaken since Athlon gets to 1.73GHz with just 10 stages and adding 2 more at 0.18u would get it to 2.07GHz assuming it is at least as well balanced as Athlon. With 28 stages, P4 at 0.18u only got to 2GHz or 70MHz a stage. He must think AMD can not do as well as it has proven to. Otherwise, he would have to admit how badly he and Intel were mistaken by their poor design decisions. The real reason Intel needs those repeaters (or boosters if you like that term better) is that they are trying to have 50% more clock on a chip twice as big. That means that they need two stages to move data around while AMD only needs one. This shows that the high clock solution does not work beyond a given point and 28 stages is far beyond that point for general purpose computing.< Up until Intel started with the P4, the industry consensus was that optimum performance would be achieved with a pipeline of between 8 and 12 stages, depending upon the complexity of the ISA. Longer pipelines could lead to higher clock rates, but the cost to IPC would negate this increased clock rate.

To: pgerassi who wrote (73888)	3/7/2002 2:26:30 PM
From: Petz	Respond to of 275872

Pete, the poor design decisions you eloquently described have been nearly equalized by their tremendous advantage in manufacturing capability (volume, low cost) and process technology (it got to 0.13u technology 4-9 months before AMD). AMD is trying to reduce Intel's manufacturing/process advantage by being the first to utilize SOI and by teaming with partners. At this point SOI looks like a high risk gamble that will pay off. Petz