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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: jcholewa who wrote (73897)	3/7/2002 2:11:06 PM
From: eCo	Respond to of 275872

Pete & JC:It is really, really unfair to make false statements about Paul. Paul likes AMD and he likes the Athlon. Maybe he doesn't like the changes that are being made for the Hammer (I don't get that impression from what I've seen him write, but you have, apparently). That doesn't mean he hates AMD and has some sort of agenda for Intel! I second this. Last I heard, his personal system used an Athlon. eCo

To: jcholewa who wrote (73897)	3/7/2002 9:39:05 PM
From: pgerassi	Read Replies (2) \| Respond to of 275872

Dear JC: The problem is that he thought the P4 was great. It failed to live up to it's hype. He fell for that hype hook line and sinker. The is no need for Athlon to include stages for wire delay due to first its small size, second its operation at lower frequencies, and lastly because of the larger length well balanced stages it uses. The first two are a factor of 0.8x and 0.85x respectively which yields a difference in P4 to Athlon wire delay of 3 to 2. This is excerbated by shorter stages as more time is taken percentage wise in the needed buffers between each stage. Some stages in P4 that operate at 2x clock can only do about two levels of logic in them. This is where the buffers take from 33% to 50% of the cycle just to store the results. So the actual allotted time for actual wire or interconnect delay is at most 1/2 the time in the P4 than on the Athlon. And the P4 has less time percentage wise as the process scales smaller compared to the Athlon. Hammer will lower this ratio but, not by much. The wider issue of Hammer will offset this as well as regards to performance. Another set of mitigating factors for Athlon is that AMD uses local interconnect (shorter needed interconnect), uses copper (comparison between 0.18u processes), uses an extra cycle for L1 caches (allows for more lookup time and more wayness) and has an additional interconnect layer (more shorter routing choices). This will further retard the need for interconnect delay stages. Another could be that AMD does a better job of functional layout where the stages that are neighbors pipeline wise are neighbors physically. All in all, DeMonde is barking up the wrong tree and where are his blasts against P4 for the poor design choices? He should at least blast P4 for its large physical size, its overlong pipeline, tiny caches and double speed ALUs that make it scale even worse than it could otherwise. He seems to forget that the longest stage, timewise, in a pipeline determines its eventual speed. Matter of fact if you look at NW you see a lot of unused silicon area. Perhaps it's their way of mitigating the hot spot thermal limitations that NW has just like its ancestor. That Athlon speeds up when thermally cooled is a big strike against the wire delay theory. Theory is good but, experimentation and empirical evidence trumps it every time. Pete